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Searched refs:phy_write (Results 1 – 25 of 41) sorted by relevance

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/linux/drivers/net/ethernet/ibm/emac/
H A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c142 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
324 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
325 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
326 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
327 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
328 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
329 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
330 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
346 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
347 phy_write(phy, CN(priv->cfg.cn), DPHY_CN); in mixel_dphy_set_pll_params()
[all …]
/linux/arch/powerpc/platforms/85xx/
H A Dmpc85xx_mds.c67 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
72 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in mpc8568_fixup_125_clock()
82 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
93 err = phy_write(phydev,29, 0x0006); in mpc8568_mds_phy_fixups()
104 err = phy_write(phydev,30, temp); in mpc8568_mds_phy_fixups()
109 err = phy_write(phydev,29, 0x000a); in mpc8568_mds_phy_fixups()
126 err = phy_write(phydev,30,temp); in mpc8568_mds_phy_fixups()
138 err = phy_write(phydev,16,temp); in mpc8568_mds_phy_fixups()
/linux/arch/arm/mach-imx/
H A Dmach-imx7d.c20 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
21 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
22 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
23 phy_write(dev, 0x1f, 0x71b7); in bcm54220_phy_fixup()
H A Dmach-imx6q.c28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
/linux/drivers/net/phy/
H A Dmicrochip.c225 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
277 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
281 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
282 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
339 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
343 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ in lan88xx_link_change_notify()
345 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */ in lan88xx_link_change_notify()
353 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
H A Ddp83869.c222 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
224 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
350 return phy_write(phydev, MII_DP83869_MICR, val_micr); in dp83869_set_wol()
634 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); in dp83869_configure_rgmii()
723 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); in dp83869_configure_mode()
733 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
738 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); in dp83869_configure_mode()
760 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
771 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
777 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
[all …]
H A Dsmsc.c75 rc = phy_write(phydev, MII_LAN83C185_IM, in smsc_phy_config_intr()
78 rc = phy_write(phydev, MII_LAN83C185_IM, 0); in smsc_phy_config_intr()
149 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc); in smsc_phy_reset()
204 phy_write(phydev, SPECIAL_CTRL_STS, rc); in lan87xx_config_aneg()
254 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
274 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
H A Ddp83867.c263 phy_write(phydev, MII_DP83867_MICR, val_micr); in dp83867_set_wol()
332 err = phy_write(phydev, MII_DP83867_MICR, micr_status); in dp83867_config_intr()
335 err = phy_write(phydev, MII_DP83867_MICR, micr_status); in dp83867_config_intr()
763 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); in dp83867_config_init()
787 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); in dp83867_config_init()
869 phy_write(phydev, DP83867_CFG3, val); in dp83867_config_init()
897 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); in dp83867_phy_reset()
917 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); in dp83867_phy_reset()
H A Dintel-xway.c243 err = phy_write(phydev, XWAY_MDIO_LED, in xway_gphy_init_leds()
284 err = phy_write(phydev, XWAY_MDIO_IMASK, 0); in xway_gphy_config_init()
310 err = phy_write(phydev, MII_CTRL1000, reg); in xway_gphy14_config_aneg()
336 err = phy_write(phydev, XWAY_MDIO_IMASK, mask); in xway_gphy_config_intr()
338 err = phy_write(phydev, XWAY_MDIO_IMASK, mask); in xway_gphy_config_intr()
H A Dbroadcom.c120 phy_write(phydev, MII_CTRL1000, val); in bcm54210e_config_init()
468 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
476 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
611 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); in bcm54xx_suspend()
877 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in brcm_fet_config_init()
917 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
1000 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
1003 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
1038 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN); in brcm_fet_suspend()
H A Ddp83822.c346 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); in dp83822_config_intr()
364 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); in dp83822_config_intr()
375 err = phy_write(phydev, MII_DP83822_MISR1, 0); in dp83822_config_intr()
379 err = phy_write(phydev, MII_DP83822_MISR2, 0); in dp83822_config_intr()
390 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); in dp83822_config_intr()
446 ret = phy_write(phydev, MII_DP83822_CTRL_2, in dp83822_read_status()
734 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); in dp83822_phy_reset()
H A Dmicrel.c543 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); in kszphy_extended_write()
544 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); in kszphy_extended_write()
550 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); in kszphy_extended_read()
580 phy_write(phydev, MII_KSZPHY_CTRL, temp); in kszphy_config_intr()
588 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL); in kszphy_config_intr()
590 err = phy_write(phydev, MII_KSZPHY_INTCS, 0); in kszphy_config_intr()
631 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); in kszphy_rmii_clk_sel()
657 rc = phy_write(phydev, reg, temp); in kszphy_setup_led()
676 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); in kszphy_broadcast_disable()
695 ret = phy_write(phydev, MII_KSZPHY_OMSO, in kszphy_nand_tree_disable()
[all …]
/linux/drivers/net/phy/qcom/
H A Dqcom-phy-lib.c21 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_read()
43 return phy_write(phydev, AT803X_DEBUG_DATA, val); in at803x_debug_reg_mask()
51 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_write()
55 return phy_write(phydev, AT803X_DEBUG_DATA, data); in at803x_debug_reg_write()
189 err = phy_write(phydev, AT803X_INTR_ENABLE, value); in at803x_config_intr()
191 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); in at803x_config_intr()
475 return phy_write(phydev, AT803X_CDT, cdt_start); in at803x_cdt_start()
/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_ethtool.c73 phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_MDIX); in hns_get_mdix_mode()
82 phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_COPPER); in hns_get_mdix_mode()
1000 retval = phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_LED); in hns_phy_led_set()
1001 retval |= phy_write(phy_dev, HNS_LED_FC_REG, value); in hns_phy_led_set()
1002 retval |= phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_COPPER); in hns_phy_led_set()
1028 ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, in hns_set_phys_id()
1035 ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, in hns_set_phys_id()
1051 ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, in hns_set_phys_id()
1056 ret = phy_write(phy_dev, HNS_LED_FC_REG, in hns_set_phys_id()
1061 ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, in hns_set_phys_id()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c363 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
366 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
385 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
388 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
564 phy_write(phydev, 0x17, 0x2138); in rtl8211_config_aneg()
565 phy_write(phydev, 0x0e, 0x0260); in rtl8211_config_aneg()
567 phy_write(phydev, 0x17, 0x2108); in rtl8211_config_aneg()
568 phy_write(phydev, 0x0e, 0x0000); in rtl8211_config_aneg()
1062 phy_write(phydev, MII_MMD_DATA, BIT(9)); in rtl8211b_suspend()
1069 phy_write(phydev, MII_MMD_DATA, 0); in rtl8211b_resume()
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c827 phy_write(phy_data->phydev, 0x16, 0x0001); in xgbe_phy_finisar_phy_quirks()
828 phy_write(phy_data->phydev, 0x00, 0x9140); in xgbe_phy_finisar_phy_quirks()
829 phy_write(phy_data->phydev, 0x16, 0x0000); in xgbe_phy_finisar_phy_quirks()
832 phy_write(phy_data->phydev, 0x1b, 0x9084); in xgbe_phy_finisar_phy_quirks()
833 phy_write(phy_data->phydev, 0x09, 0x0e00); in xgbe_phy_finisar_phy_quirks()
834 phy_write(phy_data->phydev, 0x00, 0x8140); in xgbe_phy_finisar_phy_quirks()
835 phy_write(phy_data->phydev, 0x04, 0x0d01); in xgbe_phy_finisar_phy_quirks()
836 phy_write(phy_data->phydev, 0x00, 0x9140); in xgbe_phy_finisar_phy_quirks()
876 phy_write(phy_data->phydev, 0x18, 0x7007); in xgbe_phy_belfuse_phy_quirks()
878 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); in xgbe_phy_belfuse_phy_quirks()
[all …]
/linux/drivers/net/ethernet/realtek/
H A Dr8169_firmware.h21 rtl_fw_write_t phy_write; member
/linux/include/linux/dsa/
H A Dlan9303.h9 int (*phy_write)(struct lan9303 *chip, int addr, member
/linux/drivers/net/dsa/mv88e6xxx/
H A Dphy.c52 if (!chip->info->ops->phy_write) in mv88e6xxx_phy_write()
55 return chip->info->ops->phy_write(chip, bus, addr, reg, val); in mv88e6xxx_phy_write()
H A Dchip.c3789 if (!chip->info->ops->phy_write) in mv88e6xxx_mdio_write()
3793 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); in mv88e6xxx_mdio_write()
4203 .phy_write = mv88e6185_phy_ppu_write,
4247 .phy_write = mv88e6185_phy_ppu_write,
4280 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4327 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4367 .phy_write = mv88e6185_phy_ppu_write,
4410 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4471 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4519 .phy_write = mv88e6165_phy_write,
[all …]
/linux/drivers/net/dsa/
H A Dlan9303_mdio.c78 .phy_write = lan9303_mdio_phy_write,
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_common.h162 void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value); member
H A Dphy_common.c287 if (dev->phy.ops->phy_write) in b43_phy_write()
288 return dev->phy.ops->phy_write(dev, reg, value); in b43_phy_write()
/linux/drivers/net/dsa/realtek/
H A Drtl83xx.c59 return priv->ops->phy_write(priv, addr, regnum, val); in rtl83xx_user_mdio_write()

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