Home
last modified time | relevance | path

Searched refs:phy_write (Results 1 – 25 of 46) sorted by relevance

12

/linux/drivers/net/ethernet/ibm/emac/
H A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c142 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
324 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
325 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
326 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
327 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
328 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
329 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
330 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
346 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
347 phy_write(phy, CN(priv->cfg.cn), DPHY_CN); in mixel_dphy_set_pll_params()
[all …]
/linux/drivers/net/phy/
H A Dbcm7xxx.c79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
350 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
355 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
[all …]
H A Ddp83tc811.c217 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
232 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
244 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
255 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
316 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
321 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
337 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
340 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
H A Ddp83869.c223 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
225 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
351 return phy_write(phydev, MII_DP83869_MICR, val_micr); in dp83869_set_wol()
635 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); in dp83869_configure_rgmii()
724 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); in dp83869_configure_mode()
734 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
739 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); in dp83869_configure_mode()
761 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
772 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
778 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
[all …]
H A Dbcm-phy-lib.c111 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK | in bcm54xx_auxctl_read()
119 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
129 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
136 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
153 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
160 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
198 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
201 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
244 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow)); in bcm_phy_read_shadow()
252 return phy_write(phydev, MII_BCM54XX_SHD, in bcm_phy_write_shadow()
[all …]
H A Dmarvell.c371 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page); in marvell_set_page()
396 err = phy_write(phydev, MII_M1011_IMASK, in marvell_config_intr()
399 err = phy_write(phydev, MII_M1011_IMASK, in marvell_config_intr()
461 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, in marvell_config_aneg()
495 err = phy_write(phydev, 0x1d, 0x1f); in m88e1101_config_aneg()
499 err = phy_write(phydev, 0x1e, 0x200c); in m88e1101_config_aneg()
503 err = phy_write(phydev, 0x1d, 0x5); in m88e1101_config_aneg()
507 err = phy_write(phydev, 0x1e, 0); in m88e1101_config_aneg()
511 err = phy_write(phydev, 0x1e, 0x100); in m88e1101_config_aneg()
956 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); in m88e1111_config_init_rgmii()
[all …]
H A Dsmsc.c75 rc = phy_write(phydev, MII_LAN83C185_IM, in smsc_phy_config_intr()
78 rc = phy_write(phydev, MII_LAN83C185_IM, 0); in smsc_phy_config_intr()
149 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc); in smsc_phy_reset()
204 phy_write(phydev, SPECIAL_CTRL_STS, rc); in lan87xx_config_aneg()
254 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
274 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
H A Dbroadcom.c120 phy_write(phydev, MII_CTRL1000, val); in bcm54210e_config_init()
468 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
476 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
616 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); in bcm54xx_suspend()
882 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in brcm_fet_config_init()
922 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
1005 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
1008 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
1043 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN); in brcm_fet_suspend()
H A Dmicrel.c557 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); in kszphy_extended_write()
558 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); in kszphy_extended_write()
564 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); in kszphy_extended_read()
594 phy_write(phydev, MII_KSZPHY_CTRL, temp); in kszphy_config_intr()
602 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL); in kszphy_config_intr()
604 err = phy_write(phydev, MII_KSZPHY_INTCS, 0); in kszphy_config_intr()
645 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); in kszphy_rmii_clk_sel()
671 rc = phy_write(phydev, reg, temp); in kszphy_setup_led()
690 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); in kszphy_broadcast_disable()
709 ret = phy_write(phydev, MII_KSZPHY_OMSO, in kszphy_nand_tree_disable()
[all …]
H A Ddp83640.c248 phy_write(phydev, regnum, val); in ext_write()
604 phy_write(phydev, PAGESEL, 0); in enable_broadcast()
610 phy_write(phydev, PHYCR2, val); in enable_broadcast()
611 phy_write(phydev, PAGESEL, init_page); in enable_broadcast()
1058 err = phy_write(phydev, MII_DP83640_MISR, misr); in dp83640_config_intr()
1068 return phy_write(phydev, MII_DP83640_MICR, micr); in dp83640_config_intr()
1076 err = phy_write(phydev, MII_DP83640_MICR, micr); in dp83640_config_intr()
1088 err = phy_write(phydev, MII_DP83640_MISR, misr); in dp83640_config_intr()
H A Dmicrochip_t1.c356 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val); in lan937x_dsp_workaround()
376 rc = phy_write(phydev, offset, val); in access_ereg()
384 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val); in access_ereg()
400 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg); in access_ereg()
695 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); in lan87xx_phy_config_intr()
717 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); in lan87xx_phy_config_intr()
726 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); in lan87xx_phy_config_intr()
/linux/arch/powerpc/platforms/85xx/
H A Dmpc85xx_mds.c67 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
72 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in mpc8568_fixup_125_clock()
82 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
93 err = phy_write(phydev,29, 0x0006); in mpc8568_mds_phy_fixups()
104 err = phy_write(phydev,30, temp); in mpc8568_mds_phy_fixups()
109 err = phy_write(phydev,29, 0x000a); in mpc8568_mds_phy_fixups()
126 err = phy_write(phydev,30,temp); in mpc8568_mds_phy_fixups()
138 err = phy_write(phydev,16,temp); in mpc8568_mds_phy_fixups()
/linux/arch/arm/mach-imx/
H A Dmach-imx7d.c20 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
21 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
22 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
23 phy_write(dev, 0x1f, 0x71b7); in bcm54220_phy_fixup()
H A Dmach-imx6q.c28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
/linux/drivers/net/phy/qcom/
H A Dqcom-phy-lib.c21 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_read()
43 return phy_write(phydev, AT803X_DEBUG_DATA, val); in at803x_debug_reg_mask()
51 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_write()
55 return phy_write(phydev, AT803X_DEBUG_DATA, data); in at803x_debug_reg_write()
189 err = phy_write(phydev, AT803X_INTR_ENABLE, value); in at803x_config_intr()
191 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); in at803x_config_intr()
475 return phy_write(phydev, AT803X_CDT, cdt_start); in at803x_cdt_start()
H A Dat803x.c253 phy_write(phydev, MII_BMCR, context->bmcr); in at803x_context_restore()
254 phy_write(phydev, MII_ADVERTISE, context->advertise); in at803x_context_restore()
255 phy_write(phydev, MII_CTRL1000, context->control1000); in at803x_context_restore()
256 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); in at803x_context_restore()
257 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); in at803x_context_restore()
258 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); in at803x_context_restore()
679 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in at803x_cable_test_autoneg()
680 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); in at803x_cable_test_autoneg()
948 phy_write(phydev, MII_CTRL1000, 0); in at8031_cable_test_start()
/linux/drivers/net/ethernet/realtek/
H A Dr8169_firmware.h21 rtl_fw_write_t phy_write; member
/linux/include/linux/dsa/
H A Dlan9303.h9 int (*phy_write)(struct lan9303 *chip, int addr, member
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c827 phy_write(phy_data->phydev, 0x16, 0x0001); in xgbe_phy_finisar_phy_quirks()
828 phy_write(phy_data->phydev, 0x00, 0x9140); in xgbe_phy_finisar_phy_quirks()
829 phy_write(phy_data->phydev, 0x16, 0x0000); in xgbe_phy_finisar_phy_quirks()
832 phy_write(phy_data->phydev, 0x1b, 0x9084); in xgbe_phy_finisar_phy_quirks()
833 phy_write(phy_data->phydev, 0x09, 0x0e00); in xgbe_phy_finisar_phy_quirks()
834 phy_write(phy_data->phydev, 0x00, 0x8140); in xgbe_phy_finisar_phy_quirks()
835 phy_write(phy_data->phydev, 0x04, 0x0d01); in xgbe_phy_finisar_phy_quirks()
836 phy_write(phy_data->phydev, 0x00, 0x9140); in xgbe_phy_finisar_phy_quirks()
876 phy_write(phy_data->phydev, 0x18, 0x7007); in xgbe_phy_belfuse_phy_quirks()
878 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); in xgbe_phy_belfuse_phy_quirks()
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dphy.c52 if (!chip->info->ops->phy_write) in mv88e6xxx_phy_write()
55 return chip->info->ops->phy_write(chip, bus, addr, reg, val); in mv88e6xxx_phy_write()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c831 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
834 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
853 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
856 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
1032 phy_write(phydev, 0x17, 0x2138); in rtl8211_config_aneg()
1033 phy_write(phydev, 0x0e, 0x0260); in rtl8211_config_aneg()
1035 phy_write(phydev, 0x17, 0x2108); in rtl8211_config_aneg()
1036 phy_write(phydev, 0x0e, 0x0000); in rtl8211_config_aneg()
1639 phy_write(phydev, MII_MMD_DATA, BIT(9)); in rtl8211b_suspend()
1646 phy_write(phydev, MII_MMD_DATA, 0); in rtl8211b_resume()
[all …]
/linux/drivers/net/dsa/
H A Dlan9303_mdio.c78 .phy_write = lan9303_mdio_phy_write,
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_common.h162 void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value); member
H A Dphy_common.c287 if (dev->phy.ops->phy_write) in b43_phy_write()
288 return dev->phy.ops->phy_write(dev, reg, value); in b43_phy_write()

12