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Searched refs:pextp_tl_ck_parents (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c83 static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8", variable
149 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
152 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
154 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
156 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
H A Dclk-mt7986-topckgen.c94 static const char *const pextp_tl_ck_parents[] __initconst = { variable
191 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
H A Dclk-mt7981-topckgen.c156 static const char * const pextp_tl_ck_parents[] __initconst = { variable
308 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,