Searched refs:pd_info (Results 1 – 3 of 3) sorted by relevance
331 struct tpmi_per_power_domain_info *pd_info, in sst_add_perf_profiles() argument338 pd_info->perf_levels = devm_kcalloc(dev, levels, sizeof(struct perf_level), GFP_KERNEL); in sst_add_perf_profiles()339 if (!pd_info->perf_levels) in sst_add_perf_profiles()342 pd_info->ratio_unit = pd_info->pp_header.ratio_unit; in sst_add_perf_profiles()343 pd_info->avx_levels = SST_MAX_AVX_LEVELS; in sst_add_perf_profiles()344 pd_info->pp_block_size = pd_info->pp_header.block_size; in sst_add_perf_profiles()347 *((u64 *)&pd_info->feature_offsets) = readq(pd_info->sst_base + in sst_add_perf_profiles()348 pd_info->sst_header.pp_offset + in sst_add_perf_profiles()351 perf_level_offsets = readq(pd_info->sst_base + pd_info->sst_header.pp_offset + in sst_add_perf_profiles()361 pd_info->perf_levels[i].mmio_offset = pd_info->sst_header.pp_offset + offset; in sst_add_perf_profiles()[all …]
359 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_domain_is_idle() local363 return (val & pd_info->idle_mask) == pd_info->idle_mask; in rockchip_pmu_domain_is_idle()376 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_ungate_clk() local379 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16; in rockchip_pmu_ungate_clk()381 if (!pd_info->clk_ungate_mask) in rockchip_pmu_ungate_clk()387 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) : in rockchip_pmu_ungate_clk()397 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_set_idle_request() local400 u32 pd_req_offset = pd_info->req_offset; in rockchip_pmu_set_idle_request()406 if (pd_info->req_mask == 0) in rockchip_pmu_set_idle_request()408 else if (pd_info->req_w_mask) in rockchip_pmu_set_idle_request()[all …]
2293 struct MR_PD_INFO *pd_info; member