Searched refs:optimal_dcfclk_for_uclk (Results 1 – 1 of 1) sorted by relevance
2270 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local2326 &optimal_dcfclk_for_uclk[i], NULL); in dcn30_update_bw_bounding_box()2328 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()2329 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()2336 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box()2359 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box()2363 …if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk… in dcn30_update_bw_bounding_box()2364 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()2378 optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2379 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()