| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | pg_cntl.h | 46 void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on);
|
| H A D | hw_shared.h | 91 int opp_inst; member
|
| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 358 unsigned int opp_inst, bool power_on) in pg_cntl35_opp_pg_control() argument
363 if (opp_inst < MAX_PIPES) in pg_cntl35_opp_pg_control()
364 pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on; in pg_cntl35_opp_pg_control()
|
| H A D | dcn35_pg_cntl.h | 181 unsigned int opp_inst, bool power_on);
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 1644 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,
1649 memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES); in hwss_add_optc_set_odm_bypass()
2185 int opp_inst; in hwss_wait_for_outstanding_hw_updates()
2211 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { in hwss_set_odm_combine()
2212 if ((dc->res_pool->opps[opp_inst] != NULL) && in hwss_set_odm_combine() local
2213 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { in hwss_set_odm_combine()
2215 dc->res_pool->opps[opp_inst] in hwss_set_odm_combine()
2161 int opp_inst; hwss_wait_for_outstanding_hw_updates() local
2273 int opp_inst = params->dsc_enable_params.opp_inst; hwss_dsc_enable() local
[all...] |
| H A D | dc_resource.c | 104 int dpp_inst, int opp_inst, int tg_inst, bool is_phantom_pipe) in capture_pipe_topology_data()
116 current_snapshot->pipe_log_lines[current_snapshot->line_count].opp_inst = opp_inst; in capture_pipe_topology_data()
103 capture_pipe_topology_data(struct dc * dc,int plane_idx,int slice_idx,int stream_idx,int dpp_inst,int opp_inst,int tg_inst,bool is_phantom_pipe) capture_pipe_topology_data() argument
|
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_psr.c | 348 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; in dmub_psr_copy_settings()
350 copy_settings_data->opp_inst = 0; in dmub_psr_copy_settings()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 1150 int opp_inst[MAX_PIPES] = {0}; in dcn32_update_odm()
1154 opp_cnt = get_odm_config(pipe_ctx, opp_inst); in dcn32_update_odm()
1159 opp_inst, opp_cnt, in dcn32_update_odm()
1294 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst }; in dcn32_resync_fifo_dccg_dio()
1301 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; in dcn32_resync_fifo_dccg_dio()
1307 opp_inst, opp_cnt, in dcn32_resync_fifo_dccg_dio()
1143 int opp_inst[MAX_PIPES] = {0}; dcn32_update_odm() local
1287 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst }; dcn32_resync_fifo_dccg_dio() local
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 615 int *opp_inst, in dcn401_trigger_3dlut_dma_load()
631 opp_inst[i] = opp_heads[i]->stream_res.opp->inst; in dcn401_set_mcm_luts()
661 int opp_inst[MAX_PIPES] = {0}; in dcn401_set_mcm_luts()
674 enable_stream_timing_calc(pipe_ctx, context, dc, &tmds_div, opp_inst, in dcn401_set_output_transfer_func()
690 opp_inst, opp_cnt, in dcn401_set_output_transfer_func()
1489 int opp_inst[MAX_PIPES] = {0}; in dcn401_dmub_hw_control_lock()
1499 opp_inst[i] = opp_heads[i]->stream_res.opp->inst; in dcn401_dmub_hw_control_lock()
1503 opp_inst, opp_head_count, in dcn401_dmub_hw_control_lock()
1626 int opp_inst[MAX_PIPES] = {0}; in dcn401_add_dsc_sequence_for_odm_change()
1636 opp_inst[ in dcn401_add_dsc_sequence_for_odm_change()
730 enable_stream_timing_calc(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc,unsigned int * tmds_div,int * opp_inst,int * opp_cnt,struct pipe_ctx * opp_heads[MAX_PIPES],bool * manual_mode,struct drr_params * params,unsigned int * event_triggers) enable_stream_timing_calc() argument
775 int opp_inst[MAX_PIPES] = {0}; dcn401_enable_stream_timing() local
1581 int opp_inst[MAX_PIPES] = {0}; dcn401_update_odm() local
1718 int opp_inst[MAX_PIPES] = {0}; dcn401_update_odm_sequence() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 828 int opp_inst[MAX_PIPES] = {0}; in dcn20_enable_stream_timing()
858 opp_inst[i] = opp_heads[i]->stream_res.opp->inst; in dcn20_enable_stream_timing()
865 opp_inst, opp_cnt, odm_slice_width, in dcn20_enable_stream_timing()
928 mpc, opp_inst[i], in dcn20_enable_stream_timing()
1184 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; in dcn20_update_odm()
1189 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; in dcn20_update_odm()
1196 opp_inst, opp_cnt, in dcn20_update_odm()
826 int opp_inst[MAX_PIPES] = {0}; dcn20_enable_stream_timing() local
1180 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; dcn20_update_odm() local
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 434 int opp_inst[MAX_PIPES] = {0}; in dcn35_update_odm()
440 opp_cnt = get_odm_config(pipe_ctx, opp_inst); in dcn35_update_odm()
445 opp_inst, opp_cnt, in dcn35_update_odm()
454 mpc, opp_inst[i], in dcn35_update_odm()
433 int opp_inst[MAX_PIPES] = {0}; dcn35_update_odm() local
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 204 int opp_inst[MAX_PIPES];
240 int opp_inst;
1678 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,
198 int opp_inst[MAX_PIPES]; global() member
234 int opp_inst; global() member
|
| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 1661 uint32_t opp_inst: 3;
3661 uint8_t opp_inst;
5122 uint8_t opp_inst;
1671 uint32_t opp_inst: 3; global() member
3662 uint8_t opp_inst; global() member
5063 uint8_t opp_inst; global() member
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 2261 inst_flags.opp_inst = pipe->stream_res.opp->inst; in dcn10_cursor_lock()
|