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Searched refs:num_queue_per_pipe (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c56 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
57 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
66 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
67 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
69 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
84 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ in amdgpu_gfx_me_queue_to_bit() local
88 * num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
89 bit += pipe * num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
213 adev->gfx.mec.num_queue_per_pipe, in amdgpu_gfx_compute_queue_acquire()
224 adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_compute_queue_acquire()
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H A Damdgpu_amdkfd_gfx_v12.c406 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
407 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
487 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v12_get_cu_occupancy()
H A Damdgpu_amdkfd_gfx_v12_1.c409 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
410 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
490 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v12_1_get_cu_occupancy()
H A Damdgpu_amdkfd_gfx_v11.c67 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
845 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
846 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
926 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v11_get_cu_occupancy()
H A Damdgpu_amdkfd.c185 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
206 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
H A Damdgpu_amdkfd_gfx_v9.c75 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in kgd_gfx_v9_get_queue_mask()
962 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
963 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
1043 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v9_get_cu_occupancy()
H A Dgfx_v12_0.c1381 adev->gfx.mec.num_queue_per_pipe; in gfx_v12_0_alloc_ip_dump()
1394 adev->gfx.me.num_queue_per_pipe; in gfx_v12_0_alloc_ip_dump()
1411 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ in gfx_v12_0_sw_init() local
1420 adev->gfx.me.num_queue_per_pipe = 8; in gfx_v12_0_sw_init()
1423 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v12_0_sw_init()
1428 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v12_0_sw_init()
1431 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v12_0_sw_init()
1468 adev->gfx.mec.num_queue_per_pipe) / 2; in gfx_v12_0_sw_init()
1520 for (j = 0; j < num_queue_per_pipe; j++) { in gfx_v12_0_sw_init()
1539 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; in gfx_v12_0_sw_init()
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H A Dgfx_v11_0.c1582 adev->gfx.mec.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1595 adev->gfx.me.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1611 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ in gfx_v11_0_sw_init() local
1634 adev->gfx.me.num_queue_per_pipe = 2; in gfx_v11_0_sw_init()
1637 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1642 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1645 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v11_0_sw_init()
1832 for (j = 0; j < num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1851 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
5183 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; in gfx_v11_0_soft_reset()
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H A Dgfx_v12_1.c1292 adev->gfx.mec.num_queue_per_pipe; in gfx_v12_1_alloc_ip_dump()
1335 adev->gfx.mec.num_queue_per_pipe); in gfx_v12_1_ip_print()
1338 adev->gfx.mec.num_queue_per_pipe; in gfx_v12_1_ip_print()
1344 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v12_1_ip_print()
1391 adev->gfx.mec.num_queue_per_pipe; in gfx_v12_1_ip_dump()
1400 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v12_1_ip_dump()
1435 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v12_1_sw_init()
1449 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v12_1_sw_init()
1456 adev->gfx.mec.num_queue_per_pipe) / 2; in gfx_v12_1_sw_init()
1509 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v12_1_sw_init()
H A Dgfx_v9_4_3.c960 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_alloc_ip_dump()
997 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_4_3_sw_init()
1044 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_4_3_sw_init()
3824 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_ip_print()
3831 adev->gfx.mec.num_queue_per_pipe); in gfx_v9_4_3_ip_print()
3838 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_4_3_ip_print()
3892 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_ip_dump()
3900 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_4_3_ip_dump()
H A Damdgpu_mes.c110 adev->gfx.me.num_queue_per_pipe, in amdgpu_mes_init()
113 adev->gfx.mec.num_queue_per_pipe, in amdgpu_mes_init()
H A Dgfx_v10_0.c4730 adev->gfx.mec.num_queue_per_pipe; in gfx_v10_0_alloc_ip_dump()
4743 adev->gfx.me.num_queue_per_pipe; in gfx_v10_0_alloc_ip_dump()
4759 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ in gfx_v10_0_sw_init() local
4771 adev->gfx.me.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4774 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4786 adev->gfx.me.num_queue_per_pipe = 2; in gfx_v10_0_sw_init()
4789 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v10_0_sw_init()
4794 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4797 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4924 for (j = 0; j < num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
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H A Damdgpu_amdkfd_gfx_v10_3.c69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
H A Damdgpu_amdkfd_gfx_v10.c69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
H A Dgfx_v9_0.c2204 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_0_alloc_ip_dump()
2277 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
2393 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
7407 adev->gfx.mec.num_queue_per_pipe); in gfx_v9_ip_print()
7411 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_print()
7453 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_dump()
H A Dmes_v11_0.c479 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { in mes_v11_0_clear_hqds_on_mec_pipe()
H A Dmes_v12_0.c495 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { in mes_v12_0_clear_hqds_on_mec_pipe()
H A Dgfx_v8_0.c1919 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
1996 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device_queue_manager.c93 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe; in is_pipe_enabled()
96 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i) in is_pipe_enabled()
111 return dqm->dev->kfd->shared_resources.num_queue_per_pipe; in get_queues_per_pipe()
1974 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) in set_sched_resources()
2128 num_hw_queue_slots = dqm->dev->kfd->shared_resources.num_queue_per_pipe * in start_cpsch()
2442 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) in detect_queue_hang()