Searched refs:num_clk_values (Results 1 – 3 of 3) sorted by relevance
283 * clock is tied off and num_clk_values == 0). Without this check the in round_up_and_copy_to_next_dpm() 285 * clk_values_khz[num_clk_values - 1] with num_clk_values == 0, which in round_up_and_copy_to_next_dpm() 294 if (clock_table->num_clk_values == 0) { in round_up_and_copy_to_next_dpm() 302 if (clock_table->num_clk_values > 2) { in map_soc_min_clocks_to_dpm_fine_grained() 303 while (index < clock_table->num_clk_values && clock_table->clk_values_khz[index] < min_value) in map_soc_min_clocks_to_dpm_fine_grained() 306 if (index < clock_table->num_clk_values) { in map_soc_min_clocks_to_dpm_fine_grained() 310 } else if (clock_table->clk_values_khz[clock_table->num_clk_values - 1] >= min_value) { in map_soc_min_clocks_to_dpm_fine_grained() 366 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained() 380 for (index = 0; index < state_table->uclk.num_clk_values; inde in map_soc_min_clocks_to_dpm_coarse_grained() [all...]
111 unsigned char num_clk_values; member
7136 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in get_active_min_uclk_dpm_index() 12038 max_uclk_mhz = mode_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_values - 1] / 1000.0; in dml_core_mode_programming()