| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 39 … int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) in rv1_determine_dppclk_threshold() argument
41 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; in rv1_determine_dppclk_threshold()
42 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
43 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; in rv1_determine_dppclk_threshold()
50 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
55 if (new_clocks->dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
56 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
60 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
69 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
75 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks() local
259 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn2_update_clocks()
260 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
275 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { in dcn2_update_clocks()
276 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn2_update_clocks()
282 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); in dcn2_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 89 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks() local
116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
117 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
120 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn201_update_clocks()
121 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn201_update_clocks()
123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
124 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
127 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) in dcn201_update_clocks()
128 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn201_update_clocks()
130 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn201_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 297 …id dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) in dcn32_update_dppclk_dispclk_freq() argument
302 if (new_clocks->dppclk_khz) { in dcn32_update_dppclk_dispclk_freq()
304 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; in dcn32_update_dppclk_dispclk_freq()
305 …new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz)… in dcn32_update_dppclk_dispclk_freq()
307 if (new_clocks->dispclk_khz > 0) { in dcn32_update_dppclk_dispclk_freq()
309 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; in dcn32_update_dppclk_dispclk_freq()
310 …new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz… in dcn32_update_dppclk_dispclk_freq()
506 struct dc_clocks *new_clocks, in dcn32_auto_dpm_test_log() argument
538 dramclk_khz_override = new_clocks->dramclk_khz; in dcn32_auto_dpm_test_log()
539 fclk_khz_override = new_clocks->fclk_khz; in dcn32_auto_dpm_test_log()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 411 struct dc_clocks *new_clocks, in dcn401_auto_dpm_test_log() argument
440 dramclk_khz_override = new_clocks->dramclk_khz; in dcn401_auto_dpm_test_log()
441 fclk_khz_override = new_clocks->fclk_khz; in dcn401_auto_dpm_test_log()
445 if (!new_clocks->p_state_change_support) in dcn401_auto_dpm_test_log()
448 if (!new_clocks->fclk_p_state_change_support) in dcn401_auto_dpm_test_log()
461 new_clocks->dramclk_khz > 0 && in dcn401_auto_dpm_test_log()
462 new_clocks->fclk_khz > 0 && in dcn401_auto_dpm_test_log()
463 new_clocks->dcfclk_khz > 0 && in dcn401_auto_dpm_test_log()
464 new_clocks->dppclk_khz > 0) { in dcn401_auto_dpm_test_log()
506 new_clocks->dcfclk_khz, in dcn401_auto_dpm_test_log()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 344 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_notify_host_router_bw() local
369 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i]; in dcn35_notify_host_router_bw()
370 …if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_ro… in dcn35_notify_host_router_bw()
371 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i]; in dcn35_notify_host_router_bw()
372 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]); in dcn35_notify_host_router_bw()
383 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_update_clocks() local
395 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) in dcn35_update_clocks()
396 new_clocks->ref_dtbclk_khz = 600000; in dcn35_update_clocks()
397 else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000) in dcn35_update_clocks()
398 new_clocks->ref_dtbclk_khz = 0; in dcn35_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 198 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn3_update_clocks() local
232 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn3_update_clocks()
233 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn3_update_clocks()
235 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
236 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn3_update_clocks()
240 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn3_update_clocks()
241 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn3_update_clocks()
245 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn3_update_clocks()
247 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn3_update_clocks()
250 p_state_change_support = new_clocks->p_state_change_support; in dcn3_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 136 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rn_update_clocks() local
174 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rn_update_clocks()
175 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in rn_update_clocks()
180 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in rn_update_clocks()
181 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in rn_update_clocks()
187 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) in rn_update_clocks()
188 new_clocks->dppclk_khz = 100000; in rn_update_clocks()
194 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { in rn_update_clocks()
195 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz; in rn_update_clocks()
196 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz; in rn_update_clocks()
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