Home
last modified time | relevance | path

Searched refs:mtk_phy_set_bits (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/phy/mediatek/
H A Dphy-mtk-ufs.c65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
81 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); in ufs_mtk_phy_set_active()
96 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); in ufs_mtk_phy_set_deep_hibern()
99 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); in ufs_mtk_phy_set_deep_hibern()
103 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
104 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
107 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_deep_hibern()
111 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
112 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
[all …]
H A Dphy-mtk-tphy.c592 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); in u3_phy_params_write()
597 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); in u3_phy_params_write()
702 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); in hs_slew_rate_calibrate()
706 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in hs_slew_rate_calibrate()
718 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in hs_slew_rate_calibrate()
763 mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE); in u3_phy_instance_init()
765 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, in u3_phy_instance_init()
767 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, in u3_phy_instance_init()
778 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, in u3_phy_instance_init()
817 mtk_phy_set_bits(com + U3P_U2PHYA_RESV1, in u2_phy_pll_26m_set()
[all …]
H A Dphy-mtk-xsphy.c134 mtk_phy_set_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); in u2_phy_slew_rate_calibrate()
138 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in u2_phy_slew_rate_calibrate()
145 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in u2_phy_slew_rate_calibrate()
187 mtk_phy_set_bits(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN); in u2_phy_instance_init()
196 mtk_phy_set_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); in u2_phy_instance_power_on()
H A Dphy-mtk-io.h22 static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits) in mtk_phy_set_bits() function
H A Dphy-mtk-mipi-csi-0-5.c136 mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90); in mtk_mipi_phy_power_on()