Home
last modified time | relevance | path

Searched refs:mtk_ddp_write (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/mediatek/
H A Dmtk_ethdr.c178 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); in mtk_ethdr_layer_config()
206 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, in mtk_ethdr_layer_config()
208 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); in mtk_ethdr_layer_config()
209 mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); in mtk_ethdr_layer_config()
228 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, in mtk_ethdr_config()
231 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, in mtk_ethdr_config()
234 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, in mtk_ethdr_config()
237 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, in mtk_ethdr_config()
240 mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base, in mtk_ethdr_config()
243 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0); in mtk_ethdr_config()
[all …]
H A Dmtk_disp_ccorr.c63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
103 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], in mtk_ccorr_ctm_set()
105 mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], in mtk_ccorr_ctm_set()
107 mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], in mtk_ccorr_ctm_set()
109 mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], in mtk_ccorr_ctm_set()
111 mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, in mtk_ccorr_ctm_set()
H A Dmtk_ddp_comp.c69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write() function
137 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5); in mtk_dither_set_common()
138 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7); in mtk_dither_set_common()
139 mtk_ddp_write(cmdq_pkt, in mtk_dither_set_common()
144 mtk_ddp_write(cmdq_pkt, in mtk_dither_set_common()
150 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); in mtk_dither_set_common()
160 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE); in mtk_dither_config()
161 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, in mtk_dither_config()
226 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); in mtk_od_config()
227 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); in mtk_od_config()
[all …]
H A Dmtk_disp_aal.c77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
78 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
H A Dmtk_ddp_comp.h356 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,