| /linux/drivers/gpu/drm/msm/ |
| H A D | msm_gpu.h | 50 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
52 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
54 int (*hw_init)(struct msm_gpu *gpu);
59 int (*ucode_load)(struct msm_gpu *gpu);
61 int (*pm_suspend)(struct msm_gpu *gpu);
62 int (*pm_resume)(struct msm_gpu *gpu);
63 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
64 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
65 irqreturn_t (*irq)(struct msm_gpu *irq);
66 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
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| H A D | msm_gpu.c | 26 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail()
50 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail()
59 static int enable_clk(struct msm_gpu *gpu) in enable_clk()
71 static int disable_clk(struct msm_gpu *gpu) in disable_clk()
89 static int enable_axi(struct msm_gpu *gpu) in enable_axi()
94 static int disable_axi(struct msm_gpu *gpu) in disable_axi()
100 int msm_gpu_pm_resume(struct msm_gpu *gpu) in msm_gpu_pm_resume()
126 int msm_gpu_pm_suspend(struct msm_gpu *gpu) in msm_gpu_pm_suspend()
152 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx, in msm_gpu_show_fdinfo()
160 int msm_gpu_hw_init(struct msm_gpu *gpu) in msm_gpu_hw_init()
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| H A D | msm_drv.h | 44 struct msm_gpu;
83 struct msm_gpu *gpu;
231 int msm_perfcntr_resume(struct msm_gpu *gpu);
232 void msm_perfcntr_suspend(struct msm_gpu *gpu);
236 struct msm_perfcntr_state * msm_perfcntr_init(struct msm_gpu *gpu);
237 void msm_perfcntr_cleanup(struct msm_gpu *gpu);
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| H A D | msm_ringbuffer.h | 50 struct msm_gpu *gpu;
126 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
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| H A D | msm_mmu.h | 14 struct msm_gpu;
78 struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu, unsigned long quirks);
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| H A D | msm_ringbuffer.c | 18 struct msm_gpu *gpu = submit->gpu; in msm_job_run()
65 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, in msm_ringbuffer_new()
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| H A D | msm_fence.c | 13 static struct msm_gpu *fctx2gpu(struct msm_fence_context *fctx) in fctx2gpu()
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| H A D | msm_submitqueue.c | 10 int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sysprof) in msm_context_set_sysprof()
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| H A D | msm_gem_submit.c | 33 struct msm_gpu *gpu, struct drm_gpuvm *vm, in submit_create()
554 struct msm_gpu *gpu = priv->gpu; in msm_ioctl_gem_submit()
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| H A D | msm_gem.h | 437 struct msm_gpu *gpu;
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| H A D | msm_drv.c | 307 struct msm_gpu *gpu; in msm_ioctl_get_param()
329 struct msm_gpu *gpu; in msm_ioctl_set_param()
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| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a5xx_gpu.h | 54 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
138 int a5xx_power_init(struct msm_gpu *gpu);
139 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
141 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs()
157 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
158 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
160 void a5xx_preempt_init(struct msm_gpu *gpu);
161 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
162 void a5xx_preempt_trigger(struct msm_gpu *gpu);
163 void a5xx_preempt_irq(struct msm_gpu *gpu);
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| H A D | adreno_gpu.h | 78 struct msm_gpu *(*init)(struct drm_device *dev);
79 u64 (*get_timestamp)(struct msm_gpu *gpu);
204 struct msm_gpu base;
612 u64 adreno_private_vm_size(struct msm_gpu *gpu);
613 int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
615 int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx,
619 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
621 int adreno_hw_init(struct msm_gpu *gpu);
622 void adreno_recover(struct msm_gpu *gpu);
623 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
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| H A D | a8xx_gpu.c | 19 static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) in a8xx_aperture_slice_set()
35 static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) in a8xx_aperture_acquire()
45 static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) in a8xx_aperture_release()
53 static void a8xx_aperture_clear(struct msm_gpu *gpu) in a8xx_aperture_clear()
61 static void a8xx_write_pipe(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 offset, u32 data) in a8xx_write_pipe()
70 static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice, u32 offset) in a8xx_read_pipe_slice()
85 void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) in a8xx_gpu_get_slice_info()
130 static inline bool _a8xx_check_idle(struct msm_gpu *gpu) in _a8xx_check_idle()
148 static bool a8xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a8xx_idle()
168 void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a8xx_flush()
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| H A D | a3xx_gpu.c | 30 static void a3xx_dump(struct msm_gpu *gpu);
31 static bool a3xx_idle(struct msm_gpu *gpu);
33 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit()
87 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init()
114 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init()
362 static void a3xx_recover(struct msm_gpu *gpu) in a3xx_recover()
383 static void a3xx_destroy(struct msm_gpu *gpu) in a3xx_destroy()
397 static bool a3xx_idle(struct msm_gpu *gpu) in a3xx_idle()
415 static irqreturn_t a3xx_irq(struct msm_gpu *gpu) in a3xx_irq()
470 static void a3xx_dump(struct msm_gpu *gpu) in a3xx_dump()
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| H A D | a5xx_gpu.c | 17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb()
127 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit()
446 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) in a5xx_set_hwcg()
477 static int a5xx_me_init(struct msm_gpu *gpu) in a5xx_me_init()
519 static int a5xx_preempt_start(struct msm_gpu *gpu) in a5xx_preempt_start()
582 static int a5xx_ucode_load(struct msm_gpu *gpu) in a5xx_ucode_load()
644 static int a5xx_zap_shader_resume(struct msm_gpu *gpu) in a5xx_zap_shader_resume()
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| H A D | adreno_device.c | 68 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) in adreno_load_gpu()
72 struct msm_gpu *gpu = NULL; in adreno_load_gpu()
216 struct msm_gpu *gpu; in adreno_bind()
258 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_unbind()
309 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_runtime_resume()
318 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_runtime_suspend()
332 static void suspend_scheduler(struct msm_gpu *gpu) in suspend_scheduler()
354 static void resume_scheduler(struct msm_gpu *gpu) in resume_scheduler()
367 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_system_suspend()
394 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_system_resume()
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| H A D | a5xx_preempt.c | 40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring()
84 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer()
95 void a5xx_preempt_trigger(struct msm_gpu *gpu) in a5xx_preempt_trigger()
175 void a5xx_preempt_irq(struct msm_gpu *gpu) in a5xx_preempt_irq()
217 void a5xx_preempt_hw_init(struct msm_gpu *gpu) in a5xx_preempt_hw_init()
250 struct msm_gpu *gpu = &adreno_gpu->base; in preempt_init_ring()
292 void a5xx_preempt_fini(struct msm_gpu *gpu) in a5xx_preempt_fini()
304 void a5xx_preempt_init(struct msm_gpu *gpu) in a5xx_preempt_init()
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| H A D | adreno_gpu.c | 31 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt()
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load()
188 adreno_create_vm(struct msm_gpu *gpu, in adreno_create_vm()
195 adreno_iommu_create_vm(struct msm_gpu *gpu, in adreno_iommu_create_vm()
229 u64 adreno_private_vm_size(struct msm_gpu *gpu) in adreno_private_vm_size()
257 struct msm_gpu *gpu = &adreno_gpu->base; in adreno_check_and_reenable_stall()
283 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, in adreno_fault_handler()
360 valid_per_process_vm(struct msm_gpu *gpu, struct drm_gpuvm *vm) in valid_per_process_vm()
365 int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, in adreno_get_param()
465 int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx, in adreno_set_param()
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| H A D | a6xx_gpu.c | 19 static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) in a6xx_gmu_get_timestamp()
40 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) in fence_status_check()
61 struct msm_gpu *gpu = &adreno_gpu->base; in fenced_write()
118 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle()
136 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle()
155 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr()
168 void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_flush()
199 a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_flush_yield()
360 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a6xx_submit()
484 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a7xx_submit()
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| H A D | a6xx_gpu_state.c | 133 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init()
146 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run()
176 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read()
210 static int cx_debugbus_read(struct msm_gpu *gpu, void __iomem *cxdbg, u32 block, u32 offset, in cx_debugbus_read()
238 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, in vbif_debugbus_read()
262 static void a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu, in a6xx_get_vbif_debugbus_block()
316 static void a6xx_get_debugbus_block(struct msm_gpu *gpu, in a6xx_get_debugbus_block()
334 static void a6xx_get_cx_debugbus_block(struct msm_gpu *gpu, in a6xx_get_cx_debugbus_block()
353 static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu, in a6xx_get_debugbus_blocks()
400 static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu, in a7xx_get_debugbus_blocks()
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| H A D | a2xx_gpummu.c | 16 struct msm_gpu *gpu;
94 struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu) in a2xx_gpummu_new()
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| H A D | a6xx_gmu.c | 26 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_fault()
155 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, in a6xx_gmu_set_freq()
251 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) in a6xx_gmu_get_freq()
933 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_fw_start()
1130 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_force_off()
1173 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) in a6xx_gmu_set_initial_freq()
1187 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) in a6xx_gmu_set_initial_bw()
1203 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_secure_init()
1312 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_resume()
1489 struct msm_gpu *gpu = &a6xx_gpu->base.base; in a6xx_gmu_stop()
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| H A D | a2xx_gpu.h | 24 struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu);
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| H A D | a6xx_gpu_state.h | 418 static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
419 static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);
426 u32 (*count_fn)(struct msm_gpu *gpu);
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