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Searched refs:mode_programming (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c827 context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dispclk_khz; in wm_set_index_to_dc_wm_set()
828 context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.dcfclk_khz; in wm_set_index_to_dc_wm_set()
829 context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.uclk_khz; in wm_set_index_to_dc_wm_set()
830 context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.fclk_khz; in wm_set_index_to_dc_wm_set()
831 context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.idle.uclk_khz; in wm_set_index_to_dc_wm_set()
832 context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.idle.fclk_khz; in wm_set_index_to_dc_wm_set()
833 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.deepsleep_dcfclk_khz; in wm_set_index_to_dc_wm_set()
834 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming->fclk_pstate_supported; in wm_set_index_to_dc_wm_set()
835 context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk_pstate_supported; in wm_set_index_to_dc_wm_set()
836 context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming in wm_set_index_to_dc_wm_set()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/
H A Ddml2_internal_shared_types.h501 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out);
500 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out); global() member