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Searched refs:mmVCE_RB_WPTR (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_2_0_d.h45 #define mmVCE_RB_WPTR 0x8064 macro
H A Dvce_3_0_d.h45 #define mmVCE_RB_WPTR 0x8064 macro
H A Dvce_4_0_offset.h88 #define mmVCE_RB_WPTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v2_0.c82 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
99 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
250 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_start()
H A Dvce_v1_0.c95 return RREG32(mmVCE_RB_WPTR); in vce_v1_0_ring_get_wptr()
112 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v1_0_ring_set_wptr()
400 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v1_0_start()
H A Dvce_v3_0.c122 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
282 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()