Home
last modified time | relevance | path

Searched refs:mmUVD_RB_WPTR (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h48 #define mmUVD_RB_WPTR 0x3c2a macro
H A Duvd_7_0_offset.h102 #define mmUVD_RB_WPTR … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h224 #define mmUVD_RB_WPTR … macro
H A Dvcn_2_5_offset.h559 #define mmUVD_RB_WPTR … macro
H A Dvcn_2_0_0_offset.h936 #define mmUVD_RB_WPTR … macro
H A Dvcn_3_0_0_offset.h889 #define mmUVD_RB_WPTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v6_0.c126 return RREG32(mmUVD_RB_WPTR); in uvd_v6_0_enc_ring_get_wptr()
157 WREG32(mmUVD_RB_WPTR, in uvd_v6_0_enc_ring_set_wptr()
869 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
H A Duvd_v7_0.c124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
1118 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()