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Searched refs:mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h2562 #define mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX … macro
H A Dgc_10_3_0_offset.h2653 #define mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX … macro