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Searched refs:mmRLC_SPM_MC_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c5213 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v9_0_update_spm_vmid_internal()
5217 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v9_0_update_spm_vmid_internal()
5223 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v9_0_update_spm_vmid_internal()
5225 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v9_0_update_spm_vmid_internal()
H A Dgfx_v10_0.c8319 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v10_0_update_spm_vmid_internal()
8331 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v10_0_update_spm_vmid_internal()
8333 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v10_0_update_spm_vmid_internal()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6115 #define mmRLC_SPM_MC_CNTL … macro
H A Dgc_9_1_offset.h6337 #define mmRLC_SPM_MC_CNTL … macro
H A Dgc_9_2_1_offset.h6315 #define mmRLC_SPM_MC_CNTL … macro
H A Dgc_10_1_0_offset.h9461 #define mmRLC_SPM_MC_CNTL … macro