Searched refs:mmCP_RB_WPTR_POLL_CNTL (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mxgpu_vi.c | 82 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
213 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
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| H A D | gfx_v7_0.c | 3819 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3822 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v7_0_init_gfx_cgpg()
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| H A D | gfx_v10_0.c | 8038 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_3d_clock_gating()
8042 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_3d_clock_gating()
8098 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_coarse_grain_clock_gating()
8102 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 513 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
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| H A D | gfx_7_2_d.h | 526 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
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| H A D | gfx_8_1_d.h | 579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
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| H A D | gfx_8_0_d.h | 579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 217 #define mmCP_RB_WPTR_POLL_CNTL … macro
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| H A D | gc_9_1_offset.h | 217 #define mmCP_RB_WPTR_POLL_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 211 #define mmCP_RB_WPTR_POLL_CNTL … macro
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| H A D | gc_10_1_0_offset.h | 2219 #define mmCP_RB_WPTR_POLL_CNTL … macro
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| H A D | gc_10_3_0_offset.h | 2302 #define mmCP_RB_WPTR_POLL_CNTL 0x0f62 macro
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