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Searched refs:mmCP_CPC_IC_BASE_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu8_smumgr.c198 mmCP_CPC_IC_BASE_CNTL); in smu8_load_mec_firmware()
204 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); in smu8_load_mec_firmware()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_d.h348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
H A Dgfx_8_0_d.h348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2607 #define mmCP_CPC_IC_BASE_CNTL … macro
H A Dgc_9_1_offset.h2877 #define mmCP_CPC_IC_BASE_CNTL … macro
H A Dgc_9_2_1_offset.h2811 #define mmCP_CPC_IC_BASE_CNTL … macro
H A Dgc_10_1_0_offset.h10293 #define mmCP_CPC_IC_BASE_CNTL … macro