Searched refs:mmBIF_BX_PF0_MAILBOX_INT_CNTL (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mxgpu_ai.c | 243 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
247 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq()
301 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
305 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_rcv_irq()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| H A D | nbio_6_1_offset.h | 2620 #define mmBIF_BX_PF0_MAILBOX_INT_CNTL … macro
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