| /linux/drivers/net/ethernet/ti/icssg/ |
| H A D | icssg_classifier.c | 205 static void rx_class_ft1_set_start_len(struct regmap *miig_rt, int slice, in rx_class_ft1_set_start_len() argument
212 regmap_write(miig_rt, offset, val); in rx_class_ft1_set_start_len()
215 static void rx_class_ft1_set_da(struct regmap *miig_rt, int slice, in rx_class_ft1_set_da() argument
221 regmap_write(miig_rt, offset, (u32)(addr[0] | addr[1] << 8 | in rx_class_ft1_set_da()
224 regmap_write(miig_rt, offset, (u32)(addr[4] | addr[5] << 8)); in rx_class_ft1_set_da()
227 static void rx_class_ft1_set_da_mask(struct regmap *miig_rt, int slice, in rx_class_ft1_set_da_mask() argument
233 regmap_write(miig_rt, offset, (u32)(addr[0] | addr[1] << 8 | in rx_class_ft1_set_da_mask()
236 regmap_write(miig_rt, offset, (u32)(addr[4] | addr[5] << 8)); in rx_class_ft1_set_da_mask()
239 static void rx_class_ft1_cfg_set_type(struct regmap *miig_rt, int slice, int n, in rx_class_ft1_cfg_set_type() argument
245 regmap_update_bits(miig_rt, offset, FT1_CFG_MASK(n), in rx_class_ft1_cfg_set_type()
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| H A D | icssg_mii_cfg.c | 45 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac) in icssg_update_rgmii_cfg() argument
55 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val); in icssg_update_rgmii_cfg()
61 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val); in icssg_update_rgmii_cfg()
67 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask, in icssg_update_rgmii_cfg()
72 void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if) in icssg_miig_set_interface_mode() argument
84 regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val); in icssg_miig_set_interface_mode()
85 regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val); in icssg_miig_set_interface_mode()
88 u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift) in icssg_rgmii_cfg_get_bitfield() argument
92 regmap_read(miig_rt, RGMII_CFG_OFFSET, &val); in icssg_rgmii_cfg_get_bitfield()
99 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii) in icssg_rgmii_get_speed() argument
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| H A D | icssg_queues.c | 23 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt); in icssg_queue_pop()
27 regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val); in icssg_queue_pop()
38 regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr); in icssg_queue_push()
49 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, ®); in icssg_queue_level()
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| H A D | icssg_mii_rt.h | 145 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac);
146 u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift);
147 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii);
148 u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii);
149 void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if);
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| H A D | icssg_config.c | 170 struct regmap *miig_rt = prueth->miig_rt; in icssg_miig_queues_init() local
181 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
186 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
189 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, in icssg_miig_queues_init()
220 regmap_write(miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, in icssg_miig_queues_init()
467 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, in icssg_init_emac_mode()
469 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK, in icssg_init_emac_mode()
472 regmap_write(prueth->miig_rt, FDB_GEN_CFG2, (FDB_PRU0_EN | FDB_PRU1_EN | FDB_HOST_EN)); in icssg_init_emac_mode()
480 icssg_class_set_host_mac_addr(prueth->miig_rt, mac); in icssg_init_emac_mode()
490 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, in icssg_init_fw_offload_mode()
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| H A D | icssg_stats.c | 39 regmap_read(prueth->miig_rt, in emac_update_hardware_stats()
42 regmap_write(prueth->miig_rt, in emac_update_hardware_stats()
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