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Searched refs:miig_rt (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_mii_cfg.c45 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac) in icssg_update_rgmii_cfg() argument
55 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val); in icssg_update_rgmii_cfg()
61 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val); in icssg_update_rgmii_cfg()
67 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask, in icssg_update_rgmii_cfg()
72 void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if) in icssg_miig_set_interface_mode() argument
84 regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val); in icssg_miig_set_interface_mode()
85 regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val); in icssg_miig_set_interface_mode()
88 u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift) in icssg_rgmii_cfg_get_bitfield() argument
92 regmap_read(miig_rt, RGMII_CFG_OFFSET, &val); in icssg_rgmii_cfg_get_bitfield()
99 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii) in icssg_rgmii_get_speed() argument
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H A Dicssg_queues.c23 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt); in icssg_queue_pop()
27 regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val); in icssg_queue_pop()
38 regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr); in icssg_queue_push()
49 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &reg); in icssg_queue_level()
H A Dicssg_mii_rt.h145 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac);
146 u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift);
147 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii);
148 u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii);
149 void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if);
H A Dicssg_config.c170 struct regmap *miig_rt = prueth->miig_rt; in icssg_miig_queues_init() local
181 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
186 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
189 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, in icssg_miig_queues_init()
220 regmap_write(miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, in icssg_miig_queues_init()
467 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, in icssg_init_emac_mode()
469 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK, in icssg_init_emac_mode()
472 regmap_write(prueth->miig_rt, FDB_GEN_CFG2, (FDB_PRU0_EN | FDB_PRU1_EN | FDB_HOST_EN)); in icssg_init_emac_mode()
480 icssg_class_set_host_mac_addr(prueth->miig_rt, mac); in icssg_init_emac_mode()
490 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, in icssg_init_fw_offload_mode()
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H A Dicssg_stats.c39 regmap_read(prueth->miig_rt, in emac_update_hardware_stats()
42 regmap_write(prueth->miig_rt, in emac_update_hardware_stats()
H A Dicssg_prueth.c260 icssg_class_default(prueth->miig_rt, ICSS_SLICE0, 0, false); in prueth_emac_common_start()
261 icssg_class_default(prueth->miig_rt, ICSS_SLICE1, 0, false); in prueth_emac_common_start()
265 icssg_ft3_hsr_configurations(prueth->miig_rt, ICSS_SLICE0, prueth); in prueth_emac_common_start()
266 icssg_ft3_hsr_configurations(prueth->miig_rt, ICSS_SLICE1, prueth); in prueth_emac_common_start()
314 icssg_class_disable(prueth->miig_rt, ICSS_SLICE0); in prueth_emac_common_start()
315 icssg_class_disable(prueth->miig_rt, ICSS_SLICE1); in prueth_emac_common_start()
327 icssg_class_disable(prueth->miig_rt, ICSS_SLICE0); in prueth_emac_common_stop()
328 icssg_class_disable(prueth->miig_rt, ICSS_SLICE1); in prueth_emac_common_stop()
383 icssg_update_rgmii_cfg(prueth->miig_rt, emac); in emac_adjust_link()
1027 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); in emac_ndo_open()
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