Searched refs:mem_level (Results 1 – 2 of 2) sorted by relevance
964 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) in vegam_calculate_mclk_params() argument973 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock; in vegam_calculate_mclk_params()974 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int; in vegam_calculate_mclk_params()975 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac; in vegam_calculate_mclk_params()976 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv; in vegam_calculate_mclk_params()982 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) in vegam_populate_single_memory_level() argument994 &mem_level->MinVoltage, &mem_level->MinMvdd); in vegam_populate_single_memory_level()1000 result = vegam_calculate_mclk_params(hwmgr, clock, mem_level); in vegam_populate_single_memory_level()1005 mem_level->EnabledForThrottle = 1; in vegam_populate_single_memory_level()1006 mem_level->EnabledForActivity = 0; in vegam_populate_single_memory_level()[all …]
1162 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level) in fiji_populate_single_memory_level() argument1179 (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd); in fiji_populate_single_memory_level()1185 mem_level->EnabledForThrottle = 1; in fiji_populate_single_memory_level()1186 mem_level->EnabledForActivity = 0; in fiji_populate_single_memory_level()1187 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst; in fiji_populate_single_memory_level()1188 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst; in fiji_populate_single_memory_level()1189 mem_level->VoltageDownHyst = 0; in fiji_populate_single_memory_level()1190 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity; in fiji_populate_single_memory_level()1191 mem_level->StutterEnable = false; in fiji_populate_single_memory_level()1193 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in fiji_populate_single_memory_level()[all …]