Searched refs:max_sh_per_se (Results 1 – 14 of 14) sorted by relevance
70 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask_v12_1()95 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask_v12_1()
2308 cu->array_count = gfx_info->max_sh_per_se * in kfd_create_vcrat_image_gpu()
1659 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1676 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1723 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1739 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1756 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1774 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()3440 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()3491 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()3602 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()3607 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()[all …]
1648 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_1_get_sa_active_bitmap()1694 adev->gfx.config.max_sh_per_se; in gfx_v12_1_setup_rb()1696 adev->gfx.config.max_sh_per_se; in gfx_v12_1_setup_rb()4368 adev->gfx.config.max_sh_per_se > 2) { in gfx_v12_1_get_cu_info()4372 adev->gfx.config.max_sh_per_se); in gfx_v12_1_get_cu_info()4378 adev->gfx.config.max_sh_per_se); in gfx_v12_1_get_cu_info()4383 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_1_get_cu_info()4384 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_1_get_cu_info()4392 disable_masks[i * adev->gfx.config.max_sh_per_se + j], in gfx_v12_1_get_cu_info()
1683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()2537 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()2548 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()2552 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()2555 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()2724 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()4695 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()7906 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()7911 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()7915 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()[all …]
513 adev->gfx.config.max_sh_per_se * in gfxhub_v2_1_utcl2_harvest()
1406 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_xcc_wait_for_rlc_serdes()4142 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_4_3_get_cu_info()4147 adev->gfx.config.max_sh_per_se); in gfx_v9_4_3_get_cu_info()4153 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_get_cu_info()4160 disable_masks[i * adev->gfx.config.max_sh_per_se + j], in gfx_v9_4_3_get_cu_info()
5096 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()5108 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()5112 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()5113 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()5124 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()5151 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()5285 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()10046 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()10135 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()10136 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()[all …]
1724 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()1766 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()1768 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()5609 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_0_get_cu_info()5610 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_0_get_cu_info()
2049 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()2091 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()2093 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()7270 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()7354 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()7355 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
557 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in amdgpu_gfx_mqd_symmetrically_map_cu_mask()567 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
2019 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()2063 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
1890 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()4128 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
5655 UCHAR max_sh_per_se; member5668 UCHAR max_sh_per_se; member