| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_mqd_manager.c | 126 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { in mqd_symmetrically_map_cu_mask()
129 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); in mqd_symmetrically_map_cu_mask()
148 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask()
194 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask()
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| H A D | kfd_topology.c | 1745 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in fill_in_l2_l3_pcache()
1813 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in kfd_fill_cache_non_crat_info()
2073 gfx_info->max_sh_per_se; in kfd_topology_add_device()
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| H A D | kfd_crat.c | 2280 cu->array_count = gfx_info->max_sh_per_se * in kfd_create_vcrat_image_gpu()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atomfirmware.c | 827 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
845 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
866 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
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| H A D | gfx_v6_0.c | 1325 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()
1366 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs()
1459 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()
1464 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1468 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()
1492 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1540 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1578 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1595 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1612 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
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| H A D | gfx_v7_0.c | 1600 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1642 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1760 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1765 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1768 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1794 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
3269 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
4188 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4205 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4223 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
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| H A D | gfx_v8_0.c | 1678 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1695 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1742 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1758 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1775 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1793 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
3449 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3500 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3611 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3616 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
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| H A D | amdgpu_debugfs.c | 130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
898 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
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| H A D | amdgpu_gfx.h | 191 unsigned max_sh_per_se; member
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| H A D | gfx_v9_0.c | 1681 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
2510 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2521 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2525 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2528 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2691 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
4636 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
7859 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
7864 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
7868 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
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| H A D | gfxhub_v2_1.c | 551 adev->gfx.config.max_sh_per_se * in gfxhub_v2_1_utcl2_harvest()
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| H A D | gfx_v10_0.c | 4986 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
4998 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
5002 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
5003 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
5014 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
5041 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
5175 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
9984 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
10073 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
10074 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
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| H A D | amdgpu_atombios.c | 728 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
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| H A D | gfx_v9_4_3.c | 1461 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_xcc_wait_for_rlc_serdes()
4946 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_4_3_get_cu_info()
4951 adev->gfx.config.max_sh_per_se); in gfx_v9_4_3_get_cu_info()
4957 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_get_cu_info()
4964 disable_masks[i * adev->gfx.config.max_sh_per_se + j], in gfx_v9_4_3_get_cu_info()
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| H A D | gfx_v9_4_2.c | 1864 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_query_sq_timeout_status()
1897 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_reset_sq_timeout_status()
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| H A D | gfx_v12_0.c | 1607 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()
1649 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
1651 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
5558 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_0_get_cu_info()
5559 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_0_get_cu_info()
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| H A D | gfx_v11_0.c | 1867 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
1909 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1911 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
7052 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
7136 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7137 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
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| H A D | amdgpu_discovery.c | 1534 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1578 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
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| H A D | amdgpu_kms.c | 861 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_kms.c | 459 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()
461 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
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| H A D | si.c | 3083 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3100 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3118 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3135 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3152 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3269 rdev->config.si.max_sh_per_se, in si_gpu_init()
3273 rdev->config.si.max_sh_per_se, in si_gpu_init()
3278 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
5309 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
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| H A D | cik.c | 3181 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3198 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3216 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3234 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3336 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3341 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
5787 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6554 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
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| H A D | radeon.h | 2126 unsigned max_sh_per_se; member
2157 unsigned max_sh_per_se; member
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atomfirmware.h | 1796 uint8_t max_sh_per_se; member
1816 uint8_t max_sh_per_se; member
1841 uint8_t max_sh_per_se; member
1876 uint8_t max_sh_per_se; member
1917 uint8_t max_sh_per_se; member
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 2225 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
2251 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
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