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Searched refs:max_banks (Results 1 – 4 of 4) sorted by relevance

/linux/arch/x86/events/amd/
H A Diommu.c40 u8 max_banks; member
157 int max_banks = piommu->max_banks; in get_next_avail_iommu_bnk_cntr() local
164 for (bank = 0; bank < max_banks; bank++) { in get_next_avail_iommu_bnk_cntr()
188 int max_banks, max_cntrs; in clear_avail_iommu_bnk_cntr() local
191 max_banks = perf_iommu->max_banks; in clear_avail_iommu_bnk_cntr()
194 if ((bank > max_banks) || (cntr > max_cntrs)) in clear_avail_iommu_bnk_cntr()
431 perf_iommu->max_banks = amd_iommu_pc_get_max_banks(idx); in init_one_iommu()
435 !perf_iommu->max_banks || in init_one_iommu()
446 idx, perf_iommu->max_banks, perf_iommu->max_counters); in init_one_iommu()
/linux/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c446 u8 max_banks; member
898 cdns_ctrl->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg); in cadence_nand_get_caps()
2773 if (cs >= cdns_ctrl->caps2.max_banks) { in cadence_nand_chip_init()
2776 cs, cdns_ctrl->caps2.max_banks); in cadence_nand_chip_init()
2839 int max_cs = cdns_ctrl->caps2.max_banks; in cadence_nand_chips_init()
/linux/drivers/iommu/amd/
H A Damd_iommu_types.h772 u8 max_banks; member
H A Dinit.c1944 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
3708 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3745 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()