Home
last modified time | relevance | path

Searched refs:ixCG_SPLL_FUNC_CNTL_2 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c61 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
65 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
70 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dci_baco.c63 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
67 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
72 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dtonga_baco.c61 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
65 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
70 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dsmu7_hwmgr.c4800 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); in smu7_read_clock_registers()
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_2_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_3_d.h49 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_0_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_0_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro