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Searched refs:ivpu_dbg (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/accel/ivpu/
H A Divpu_gem_userptr.c87 ivpu_dbg(vdev, IOCTL, "Failed to pin user pages: %d\n", ret); in ivpu_create_userptr_dmabuf()
92 ivpu_dbg(vdev, IOCTL, "Pinned %d pages, expected %lu\n", pinned, nr_pages); in ivpu_create_userptr_dmabuf()
105 ivpu_dbg(vdev, IOCTL, "Failed to create sg table: %d\n", ret); in ivpu_create_userptr_dmabuf()
119 ivpu_dbg(vdev, IOCTL, "Failed to export userptr dma-buf: %d\n", ret); in ivpu_create_userptr_dmabuf()
174 ivpu_dbg(vdev, IOCTL, "Invalid BO flags: 0x%x\n", args->flags); in ivpu_bo_create_from_userptr_ioctl()
179 ivpu_dbg(vdev, IOCTL, "Userptr or size are zero: ptr %llx size %llu\n", in ivpu_bo_create_from_userptr_ioctl()
185 ivpu_dbg(vdev, IOCTL, "Userptr or size not page aligned: ptr %llx size %llu\n", in ivpu_bo_create_from_userptr_ioctl()
191 ivpu_dbg(vdev, IOCTL, "Userptr is not accessible: ptr %llx size %llu\n", in ivpu_bo_create_from_userptr_ioctl()
202 ivpu_dbg(vdev, IOCTL, "Failed to create handle for BO: %pe ctx %u size %llu flags 0x%x\n", in ivpu_bo_create_from_userptr_ioctl()
205 ivpu_dbg(vdev, BO, "Created userptr BO: handle=%u vpu_addr=0x%llx size=%llu flags=0x%x\n", in ivpu_bo_create_from_userptr_ioctl()
H A Divpu_pm.c52 ivpu_dbg(vdev, FW_BOOT, "Cold boot entry point 0x%llx", vdev->fw->cold_boot_entry_point); in ivpu_pm_prepare_cold_boot()
67 ivpu_dbg(vdev, FW_BOOT, "Warm boot entry point 0x%llx", fw->warm_boot_entry_point); in ivpu_pm_prepare_warm_boot()
258 ivpu_dbg(vdev, PM, "Suspend..\n"); in ivpu_pm_suspend_cb()
274 ivpu_dbg(vdev, PM, "Suspend done.\n"); in ivpu_pm_suspend_cb()
287 ivpu_dbg(vdev, PM, "Resume..\n"); in ivpu_pm_resume_cb()
293 ivpu_dbg(vdev, PM, "Resume done.\n"); in ivpu_pm_resume_cb()
310 ivpu_dbg(vdev, PM, "Runtime suspend..\n"); in ivpu_pm_runtime_suspend_cb()
335 ivpu_dbg(vdev, PM, "Runtime suspend done.\n"); in ivpu_pm_runtime_suspend_cb()
348 ivpu_dbg(vdev, PM, "Runtime resume..\n"); in ivpu_pm_runtime_resume_cb()
354 ivpu_dbg(vdev, PM, "Runtime resume done.\n"); in ivpu_pm_runtime_resume_cb()
[all …]
H A Divpu_job.c176 ivpu_dbg(vdev, IOCTL, "Failed to allocate command queue ID: %d\n", ret); in ivpu_cmdq_create()
187 ivpu_dbg(vdev, JOB, "Command queue %d created, ctx %d, flags 0x%08x\n", in ivpu_cmdq_create()
223 ivpu_dbg(vdev, IOCTL, "Maximum number of %u doorbells for uid %u reached\n", in ivpu_register_db()
232 ivpu_dbg(vdev, IOCTL, "Failed to allocate doorbell ID: %d\n", ret); in ivpu_register_db()
248 ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n", in ivpu_register_db()
302 ivpu_dbg(vdev, JOB, "DB %d unregistered\n", cmdq->db_id); in ivpu_cmdq_unregister()
307 ivpu_dbg(vdev, JOB, "Command queue %d destroyed, ctx %d\n", in ivpu_cmdq_unregister()
364 ivpu_dbg(vdev, IOCTL, "Failed to find command queue with ID: %u\n", cmdq_id); in ivpu_cmdq_acquire()
426 ivpu_dbg(vdev, JOB, "Context ID: %u abort\n", file_priv->ctx.id); in ivpu_context_abort_locked()
449 ivpu_dbg(vdev, JOB, "Job queue full: ctx %d cmdq %d db %d head %d tail %d\n", in ivpu_cmdq_push_job()
[all …]
H A Divpu_mmu.c313 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
317 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF); in ivpu_mmu_config_check()
321 ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF); in ivpu_mmu_config_check()
332 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
345 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size); in ivpu_mmu_cdtab_alloc()
364 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n", in ivpu_mmu_strtab_alloc()
383 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_cmdq_alloc()
402 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_evtq_alloc()
505 ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1); in ivpu_mmu_cmdq_cmd_write()
669 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]); in ivpu_mmu_strtab_link_cd()
[all …]
H A Divpu_fw_log.c53 ivpu_dbg(vdev, FW_BOOT, "Invalid header size 0x%x\n", header_size); in fw_log_from_bo()
57 ivpu_dbg(vdev, FW_BOOT, "Invalid log size 0x%x\n", size); in fw_log_from_bo()
61 ivpu_dbg(vdev, FW_BOOT, "Invalid log size 0x%x < header size 0x%x\n", in fw_log_from_bo()
71 ivpu_dbg(vdev, FW_BOOT, in fw_log_from_bo()
H A Divpu_drv.c107 ivpu_dbg(vdev, IOCTL, "User %u exceeded max ctx count %u\n", uid, in ivpu_user_limits_get()
143 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n", in ivpu_file_priv_get()
153 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id); in file_priv_unbind()
169 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n", in file_priv_release()
191 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n", in ivpu_file_priv_put()
358 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n", in ivpu_open()
380 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n", in ivpu_postclose()
434 ivpu_dbg(vdev, PM, "NPU ready message received successfully\n"); in ivpu_wait_for_ready()
642 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); in ivpu_pci_init()
649 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4); in ivpu_pci_init()
H A Divpu_ms.c56 ivpu_dbg(vdev, IOCTL, "Instance already exists (mask %#llx)\n", in ivpu_ms_start_ioctl()
77 ivpu_dbg(vdev, IOCTL, "Requested MS buffer size %llu exceeds range size %llu\n", in ivpu_ms_start_ioctl()
85 ivpu_dbg(vdev, IOCTL, "Failed to allocate MS buffer (size %llu)\n", buf_size); in ivpu_ms_start_ioctl()
186 ivpu_dbg(vdev, IOCTL, "Instance doesn't exist for mask: %#llx\n", in ivpu_ms_get_data_ioctl()
H A Divpu_hw_btrs.c146 ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config); in read_tile_config_fuse()
338 ivpu_dbg(vdev, PM, "Skipping workpoint request\n"); in ivpu_hw_btrs_wp_drive()
344 ivpu_dbg(vdev, PM, "PLL workpoint request: %u MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n", in ivpu_hw_btrs_wp_drive()
551 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", in ivpu_hw_btrs_ats_print_lnl()
638 ivpu_dbg(vdev, PM, "Set frequency range to min: %u, pn: %u, max: %u MHz\n", in ivpu_hw_btrs_cfg_freq_set()
710 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %u MHz", in ivpu_hw_btrs_irq_handler_mtl()
757 ivpu_dbg(vdev, IRQ, "Survivability IRQ\n"); in ivpu_hw_btrs_irq_handler_lnl()
764 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %u MHz", in ivpu_hw_btrs_irq_handler_lnl()
H A Divpu_drv.h98 #define ivpu_dbg(vdev, type, fmt, args...) do { \ macro
107 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
H A Divpu_ipc.c30 ivpu_dbg(vdev, IPC, in ivpu_ipc_msg_dump()
41 ivpu_dbg(vdev, JSM, in ivpu_jsm_msg_dump()
462 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); in ivpu_ipc_irq_handler()