Searched refs:internal_clk (Results 1 – 2 of 2) sorted by relevance
48 static bool internal_clk = true; variable49 module_param(internal_clk, bool, 0444);50 MODULE_PARM_DESC(internal_clk, "Use internal clock, default true (24MHz)");123 if (internal_clk) { in f81601_pci_probe()164 if (internal_clk) in f81601_pci_probe()
49 u32 internal_clk; member626 state->internal_clk = state->cfg.bw->internal; in dib7000m_demod_reset()990 value = 30 * state->internal_clk * factor; in dib7000m_autosearch_start()993 value = 100 * state->internal_clk * factor; in dib7000m_autosearch_start()996 value = 500 * state->internal_clk * factor; in dib7000m_autosearch_start()