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Searched refs:inst_idx (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c428 int inst_idx = vinst->inst; in vcn_v5_0_0_mc_resume_dpg_mode() local
432 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; in vcn_v5_0_0_mc_resume_dpg_mode()
438 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
439 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v5_0_0_mc_resume_dpg_mode()
440 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
441 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
442 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v5_0_0_mc_resume_dpg_mode()
443 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
444 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
445 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
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H A Djpeg_v4_0_5.c356 int inst_idx, uint8_t indirect) in jpeg_engine_4_0_5_dpg_clock_gating_mode() argument
367 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect); in jpeg_engine_4_0_5_dpg_clock_gating_mode()
370 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_GATE_INTERNAL_OFFSET, in jpeg_engine_4_0_5_dpg_clock_gating_mode()
421 static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v4_0_5_start_dpg_mode() argument
423 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v4_0_5_start_dpg_mode()
427 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
430 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v4_0_5_start_dpg_mode()
433 WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_start_dpg_mode()
435 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
440 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
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H A Djpeg_v4_0_3.c510 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_disable_clock_gating() argument
515 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
535 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_enable_clock_gating() argument
540 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
H A Dvcn_v2_0.c1294 int inst_idx = vinst->inst; in vcn_v2_0_pause_dpg_mode() local
1300 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1302 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1363 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
/linux/drivers/perf/
H A Dnvidia_t410_c2c_pmu.c338 u32 ctr_id, ctr_offset, filter_mask, filter_idx, inst_idx; in nv_c2c_pmu_read_counter() local
352 for_each_set_bit(inst_idx, inst_mask, c2c_pmu->data->nr_inst) { in nv_c2c_pmu_read_counter()
353 nv_c2c_pmu_check_status(c2c_pmu, inst_idx); in nv_c2c_pmu_read_counter()
362 c2c_pmu->base[inst_idx] + ctr_offset, in nv_c2c_pmu_read_counter()
369 c2c_pmu->base[inst_idx] + ctr_offset, in nv_c2c_pmu_read_counter()