Searched refs:input_clks (Results 1 – 2 of 2) sorted by relevance
392 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; member833 clk = wiz->input_clks[mux_sel->parents[i]]; in wiz_mux_clk_register()1084 rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK]); in wiz_clock_init()1109 if (wiz->input_clks[WIZ_CORE_REFCLK1]) { in wiz_clock_init()1110 rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK1]); in wiz_clock_init()1117 rate = clk_get_rate(wiz->input_clks[WIZ_EXT_REFCLK]); in wiz_clock_init()1139 wiz->input_clks[WIZ_CORE_REFCLK] = clk; in wiz_clock_probe()1147 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; in wiz_clock_probe()1155 wiz->input_clks[WIZ_EXT_REFCLK] = clk; in wiz_clock_probe()
405 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; member560 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_init()561 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_init()1166 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()1174 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()1190 sp->input_clks[PHY_CLK] = clk; in cdns_sierra_phy_clk()1192 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_clk()1224 clk_disable_unprepare(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_disable_clocks()1266 clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_configure_multilink()1267 clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_configure_multilink()