/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v4_4_2.c | 489 u32 rb_cntl, ib_cntl; in sdma_v4_4_2_inst_gfx_stop() local 498 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); in sdma_v4_4_2_inst_gfx_stop() 499 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v4_4_2_inst_gfx_stop() 500 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); in sdma_v4_4_2_inst_gfx_stop() 541 u32 rb_cntl, ib_cntl; in sdma_v4_4_2_inst_page_stop() local 549 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); in sdma_v4_4_2_inst_page_stop() 550 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, in sdma_v4_4_2_inst_page_stop() 552 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); in sdma_v4_4_2_inst_page_stop() 679 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v4_4_2_gfx_resume() local 754 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); in sdma_v4_4_2_gfx_resume() [all …]
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H A D | sdma_v2_4.c | 340 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local 347 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop() 348 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v2_4_gfx_stop() 349 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_stop() 404 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local 461 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume() 462 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); in sdma_v2_4_gfx_resume() 464 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume() 467 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_resume()
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H A D | sdma_v4_0.c | 924 u32 rb_cntl, ib_cntl; in sdma_v4_0_gfx_enable() local 931 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); in sdma_v4_0_gfx_enable() 932 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0); in sdma_v4_0_gfx_enable() 933 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); in sdma_v4_0_gfx_enable() 958 u32 rb_cntl, ib_cntl; in sdma_v4_0_page_stop() local 966 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); in sdma_v4_0_page_stop() 967 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, in sdma_v4_0_page_stop() 969 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); in sdma_v4_0_page_stop() 1092 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v4_0_gfx_resume() local 1156 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); in sdma_v4_0_gfx_resume() [all …]
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H A D | vpe_v6_1.c | 212 uint32_t ib_cntl, i; in vpe_v6_1_ring_start() local 264 ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL)); in vpe_v6_1_ring_start() 265 ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1); in vpe_v6_1_ring_start() 266 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl); in vpe_v6_1_ring_start()
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H A D | sdma_v5_2.c | 415 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_stop() local 422 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_stop() 423 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v5_2_gfx_stop() 424 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_2_gfx_stop() 538 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_resume_instance() local 670 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_resume_instance() 671 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); in sdma_v5_2_gfx_resume_instance() 673 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); in sdma_v5_2_gfx_resume_instance() 676 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_2_gfx_resume_instance() 1476 u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg; in sdma_v5_2_reset_queue() local [all …]
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H A D | sdma_v3_0.c | 516 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local 523 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop() 524 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v3_0_gfx_stop() 525 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_stop() 641 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v3_0_gfx_resume() local 731 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume() 732 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); in sdma_v3_0_gfx_resume() 734 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); in sdma_v3_0_gfx_resume() 737 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_resume()
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H A D | sdma_v5_0.c | 596 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local 603 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_stop() 604 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v5_0_gfx_stop() 605 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_stop() 720 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume_instance() local 854 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_resume_instance() 855 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); in sdma_v5_0_gfx_resume_instance() 857 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); in sdma_v5_0_gfx_resume_instance() 860 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_resume_instance() 1576 u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg; in sdma_v5_0_reset_queue() local [all …]
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H A D | sdma_v7_0.c | 427 u32 rb_cntl, ib_cntl; in sdma_v7_0_gfx_stop() local 434 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v7_0_gfx_stop() 435 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); in sdma_v7_0_gfx_stop() 436 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); in sdma_v7_0_gfx_stop() 505 u32 rb_cntl, ib_cntl; in sdma_v7_0_gfx_resume_instance() local 631 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v7_0_gfx_resume_instance() 632 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); in sdma_v7_0_gfx_resume_instance() 634 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); in sdma_v7_0_gfx_resume_instance() 637 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); in sdma_v7_0_gfx_resume_instance()
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H A D | sdma_v6_0.c | 395 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_stop() local 402 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v6_0_gfx_stop() 403 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); in sdma_v6_0_gfx_stop() 404 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); in sdma_v6_0_gfx_stop() 484 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_resume_instance() local 608 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v6_0_gfx_resume_instance() 609 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); in sdma_v6_0_gfx_resume_instance() 611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); in sdma_v6_0_gfx_resume_instance() 614 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); in sdma_v6_0_gfx_resume_instance()
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H A D | si_dma.c | 129 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local 161 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; in si_dma_start() 163 ib_cntl |= DMA_IB_SWAP_ENABLE; in si_dma_start() 165 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); in si_dma_start()
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H A D | cik_sdma.c | 430 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local 487 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; in cik_sdma_gfx_resume() 489 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; in cik_sdma_gfx_resume() 492 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in cik_sdma_gfx_resume()
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/linux/drivers/gpu/drm/radeon/ |
H A D | ni_dma.c | 189 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local 232 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; in cayman_dma_resume() 234 ib_cntl |= DMA_IB_SWAP_ENABLE; in cayman_dma_resume() 236 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); in cayman_dma_resume()
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H A D | r600_dma.c | 122 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local 153 ib_cntl = DMA_IB_ENABLE; in r600_dma_resume() 155 ib_cntl |= DMA_IB_SWAP_ENABLE; in r600_dma_resume() 157 WREG32(DMA_IB_CNTL, ib_cntl); in r600_dma_resume()
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H A D | cik_sdma.c | 367 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local 416 ib_cntl = SDMA_IB_ENABLE; in cik_sdma_gfx_resume() 418 ib_cntl |= SDMA_IB_SWAP_ENABLE; in cik_sdma_gfx_resume() 421 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); in cik_sdma_gfx_resume()
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