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Searched refs:hw_pp (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_cmd.c72 phys_enc->hw_pp->idx); in _dpu_encoder_phys_cmd_update_intf_cfg()
90 if (!phys_enc->hw_pp) in dpu_encoder_phys_cmd_pp_tx_done_irq()
102 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_phys_cmd_pp_tx_done_irq()
152 phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; in dpu_encoder_phys_cmd_atomic_mode_set()
157 phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; in dpu_encoder_phys_cmd_atomic_mode_set()
171 if (!phys_enc->hw_pp) in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
185 phys_enc->hw_pp->idx - PINGPONG_0, in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
194 phys_enc->hw_pp->idx - PINGPONG_0, in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
244 if (!phys_enc->hw_pp) { in dpu_encoder_phys_cmd_control_vblank_irq()
263 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_phys_cmd_control_vblank_irq()
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H A Ddpu_encoder.c181 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; member
346 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) in _dpu_encoder_setup_dither() argument
350 if (!hw_pp->ops.setup_dither) in _dpu_encoder_setup_dither()
362 hw_pp->ops.setup_dither(hw_pp, NULL); in _dpu_encoder_setup_dither()
369 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); in _dpu_encoder_setup_dither()
396 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); in dpu_encoder_helper_report_irq_timeout()
435 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
451 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
462 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
469 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
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H A Ddpu_encoder_phys_wb.c232 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp; in dpu_encoder_phys_wb_setup_ctl() local
240 if (mode_3d && hw_pp && hw_pp->merge_3d) in dpu_encoder_phys_wb_setup_ctl()
241 intf_cfg.merge_3d = hw_pp->merge_3d->idx; in dpu_encoder_phys_wb_setup_ctl()
246 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode) in dpu_encoder_phys_wb_setup_ctl()
247 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, in dpu_encoder_phys_wb_setup_ctl()
251 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk) in dpu_encoder_phys_wb_setup_ctl()
253 phys_enc->hw_pp->idx); in dpu_encoder_phys_wb_setup_ctl()
275 struct dpu_hw_pingpong *hw_pp; in _dpu_encoder_phys_wb_update_flush() local
284 hw_pp = phys_enc->hw_pp; in _dpu_encoder_phys_wb_update_flush()
300 hw_pp && hw_pp->merge_3d) in _dpu_encoder_phys_wb_update_flush()
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H A Ddpu_encoder_phys_vid.c305 if (intf_cfg.mode_3d && phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
306 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_phys_vid_setup_timing_engine()
318 phys_enc->hw_pp->idx); in dpu_encoder_phys_vid_setup_timing_engine()
320 if (phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
321 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); in dpu_encoder_phys_vid_setup_timing_engine()
472 phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_enable()
473 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); in dpu_encoder_phys_vid_enable()
H A Ddpu_encoder_phys.h181 struct dpu_hw_pingpong *hw_pp; member