Searched refs:hdmi_phy (Results 1 – 16 of 16) sorted by relevance
22 static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy) in mtk_hdmi_ana_fifo_en() argument25 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN); in mtk_hdmi_ana_fifo_en()29 mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable) in mtk_phy_tmds_clk_ratio() argument31 void __iomem *regs = hdmi_phy->regs; in mtk_phy_tmds_clk_ratio()33 mtk_hdmi_ana_fifo_en(hdmi_phy); in mtk_phy_tmds_clk_ratio()46 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_sel_src() local47 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_sel_src()58 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_perf() local59 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_perf()91 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_set_hw() local[all …]
52 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_prepare() local53 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_prepare()74 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_unprepare() local75 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_unprepare()96 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_set_rate() local97 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_set_rate()132 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_recalc_rate() local136 tmp = readl(hdmi_phy->regs + HDMI_CON6); in mtk_hdmi_pll_recalc_rate()153 tmp = readl(hdmi_phy->regs + HDMI_CON2); in mtk_hdmi_pll_recalc_rate()171 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) in mtk_hdmi_phy_enable_tmds() argument[all …]
22 struct hdmi_phy;58 struct hdmi_phy *phy;154 void (*powerup)(struct hdmi_phy *phy, unsigned long pixclock);155 void (*powerdown)(struct hdmi_phy *phy);168 struct hdmi_phy { struct177 static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data) in hdmi_phy_write() argument182 static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg) in hdmi_phy_read()187 int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);188 void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);189 void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long pixclock);[all …]
11 static int msm_hdmi_phy_resource_init(struct hdmi_phy *phy) in msm_hdmi_phy_resource_init()55 int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy) in msm_hdmi_phy_resource_enable()83 void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy) in msm_hdmi_phy_resource_disable()97 void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long pixclock) in msm_hdmi_phy_powerup()105 void msm_hdmi_phy_powerdown(struct hdmi_phy *phy) in msm_hdmi_phy_powerdown()144 struct hdmi_phy *phy; in msm_hdmi_phy_probe()
274 struct hdmi_phy *phy = hdmi->phy; in msm_hdmi_bridge_atomic_pre_enable()316 struct hdmi_phy *phy = hdmi->phy; in msm_hdmi_bridge_atomic_post_disable()
15 hdmi_phy.o
29 dss/hdmi_pll.o dss/hdmi_phy.o
237 phys = <&hdmi_phy>;263 hdmi_phy: hdmi-phy@10209100 { label
271 &hdmi_phy {
299 &hdmi_phy {
152 &hdmi_phy {
585 hdmi_phy: hdmi-phy@12030000 { label725 assigned-clock-parents = <&hdmi_phy>;732 phys = <&hdmi_phy>;
40 hdmi/hdmi_phy.o \
831 phys = <&hdmi_phy>;853 hdmi_phy: hdmi-phy@1ef0000 { label
1278 phys = <&hdmi_phy>;1300 hdmi_phy: hdmi-phy@1ef0000 { label
840 clock-output-names = "hdmi_phy";