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Searched refs:gvt_vgpu_err (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A Ddmabuf.c294 gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled); in vgpu_get_plane_info()
318 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
324 gvt_vgpu_err("fb size is zero\n"); in vgpu_get_plane_info()
329 gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start); in vgpu_get_plane_info()
334 gvt_vgpu_err("invalid gma addr\n"); in vgpu_get_plane_info()
452 gvt_vgpu_err("alloc dmabuf_obj failed\n"); in intel_vgpu_query_plane()
459 gvt_vgpu_err("allocate intel vgpu fb info failed\n"); in intel_vgpu_query_plane()
514 gvt_vgpu_err("invalid dmabuf id:%d\n", dmabuf_id); in intel_vgpu_get_dmabuf()
521 gvt_vgpu_err("create gvt gem obj failed\n"); in intel_vgpu_get_dmabuf()
530 gvt_vgpu_err("export dma-buf failed\n"); in intel_vgpu_get_dmabuf()
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H A Dcmd_parser.c879 gvt_vgpu_err("failed to get the 4-level shadow vm\n"); in cmd_pdp_mmio_update_handler()
892 gvt_vgpu_err("invalid shared shadow vm type\n"); in cmd_pdp_mmio_update_handler()
907 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n", in cmd_reg_handler()
923 gvt_vgpu_err("%s access to non-render register (%x)\n", in cmd_reg_handler()
936 gvt_vgpu_err("%s access to register (%x)\n", in cmd_reg_handler()
947 gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset); in cmd_reg_handler()
995 gvt_vgpu_err("try to write RO reg %x\n", in cmd_reg_handler()
1382 gvt_vgpu_err("unknown plane code %d\n", plane); in skl_decode_mi_display_flip()
1501 gvt_vgpu_err("fail to decode MI display flip command\n"); in cmd_handler_mi_display_flip()
1507 gvt_vgpu_err("invalid MI display flip command\n"); in cmd_handler_mi_display_flip()
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H A Dgtt.c776 gvt_vgpu_err("fail to allocate ppgtt shadow page\n"); in ppgtt_alloc_spt()
791 gvt_vgpu_err("fail to map dma addr\n"); in ppgtt_alloc_spt()
913 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n", in ppgtt_invalidate_spt_by_shadow_entry()
986 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n", in ppgtt_invalidate_spt()
1068 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_populate_spt_by_guest_entry()
1213 gvt_vgpu_err("GVT doesn't support 1GB entry\n"); in ppgtt_populate_shadow_entry()
1255 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_populate_spt()
1284 gvt_vgpu_err("fail to find guest page\n"); in ppgtt_handle_guest_entry_removal()
1300 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_handle_guest_entry_removal()
1335 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n", in ppgtt_handle_guest_entry_add()
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H A Dkvmgt.c156 gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n", in gvt_pin_guest_page()
192 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", in gvt_dma_map_page()
410 gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); in intel_vgpu_reg_rw_opregion()
460 gvt_vgpu_err("invalid EDID blob\n"); in handle_edid_regs()
467 gvt_vgpu_err("invalid EDID link state %d\n", in handle_edid_regs()
475 gvt_vgpu_err("EDID size is bigger than %d!\n", in handle_edid_regs()
483 gvt_vgpu_err("write read-only EDID region at offset %d\n", in handle_edid_regs()
525 gvt_vgpu_err("failed to access EDID region\n"); in intel_vgpu_reg_rw_edid()
676 gvt_vgpu_err("KVM is required to use Intel vGPU\n"); in intel_vgpu_open_device()
780 gvt_vgpu_err("Invalid aperture offset %llu\n", off); in intel_vgpu_aperture_rw()
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H A Ddebug.h30 #define gvt_vgpu_err(fmt, args...) \ macro
H A Dhandlers.c217 gvt_vgpu_err("access oob fence reg %d/%d\n", in sanitize_fence_mmio_access()
249 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", in gamw_echo_dev_rw_ia_write()
319 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); in mul_force_wake_write()
877 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); in check_fdi_rx_train_status()
936 gvt_vgpu_err("Unsupported registers %x\n", offset); in update_fdi_rx_iir_status()
1198 gvt_vgpu_err("Unsupported DP port access!\n"); in dp_aux_ch_ctl_mmio_write()
1258 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1325 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1411 gvt_vgpu_err("SBI caching meets maximum limits\n"); in write_virtual_sbi_register()
1490 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", in pvinfo_mmio_read()
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