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Searched refs:gmc (Results 1 – 25 of 80) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v2_1.c144 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
149 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
163 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_1_init_system_aperture_regs()
164 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_1_init_system_aperture_regs()
168 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
170 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
239 if (adev->gmc.translate_further) { in gfxhub_v2_1_init_cache_regs()
326 !adev->gmc.noretry); in gfxhub_v2_1_setup_vmid_config()
[all …]
H A Dgmc_v12_0.c174 adev->gmc.vm_fault.num_types = 1; in gmc_v12_0_set_irq_funcs()
175 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; in gmc_v12_0_set_irq_funcs()
178 adev->gmc.ecc_irq.num_types = 1; in gmc_v12_0_set_irq_funcs()
179 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; in gmc_v12_0_set_irq_funcs()
228 spin_lock(&adev->gmc.invalidate_lock); in gmc_v12_0_flush_vm_hub()
287 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v12_0_flush_vm_hub()
490 adev->gmc.vram_start; in gmc_v12_0_get_vm_pde()
493 if (!adev->gmc.translate_further) in gmc_v12_0_get_vm_pde()
586 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; in gmc_v12_0_set_gmc_funcs()
641 adev->gmc in gmc_v12_0_early_init()
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H A Damdgpu_gmc.c46 return adev->gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev); in amdgpu_gmc_is_pdb0_enabled()
61 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
62 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
75 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
79 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
83 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
86 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
90 amdgpu_bo_unreserve(adev->gmc in amdgpu_gmc_pdb0_alloc()
425 struct amdgpu_gmc *gmc = &adev->gmc; amdgpu_gmc_filter_faults() local
494 struct amdgpu_gmc *gmc = &adev->gmc; amdgpu_gmc_filter_faults_remove() local
997 struct amdgpu_gmc *gmc = &adev->gmc; amdgpu_gmc_noretry_set() local
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H A Dgmc_v9_0.c696 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
697 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
700 !adev->gmc.xgmi.connected_to_cpu && in gmc_v9_0_set_irq_funcs()
701 !adev->gmc.is_app_apu) { in gmc_v9_0_set_irq_funcs()
702 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
703 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
811 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
873 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
1026 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
1080 adev->gmc in gmc_v9_0_get_coherence_flags()
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H A Dgmc_v10_0.c182 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
183 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
186 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
187 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
268 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_gpu_tlb()
314 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_gpu_tlb()
461 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
558 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
559 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
623 adev->gmc in gmc_v10_0_early_init()
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H A Dgmc_v11_0.c178 adev->gmc.vm_fault.num_types = 1; in gmc_v11_0_set_irq_funcs()
179 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; in gmc_v11_0_set_irq_funcs()
182 adev->gmc.ecc_irq.num_types = 1; in gmc_v11_0_set_irq_funcs()
183 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; in gmc_v11_0_set_irq_funcs()
256 spin_lock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_gpu_tlb()
307 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_gpu_tlb()
452 if (!adev->gmc.translate_further) in gmc_v11_0_get_vm_pde()
549 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; in gmc_v11_0_set_gmc_funcs()
627 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v11_0_early_init()
628 adev->gmc in gmc_v11_0_early_init()
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H A Dgmc_v7_0.c40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
160 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v7_0_init_microcode()
164 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v7_0_init_microcode()
185 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
188 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode()
191 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v7_0_mc_load_microcode()
194 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
197 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
294 adev->gmc in gmc_v7_0_mc_program()
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H A Dgmc_v8_0.c35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v8_0_init_microcode()
266 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
295 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
364 if (!adev->gmc in gmc_v8_0_polaris_mc_load_microcode()
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H A Dgfxhub_v1_0.c58 if (adev->gmc.pdb0_bo) in gfxhub_v1_0_init_gart_aperture_regs()
59 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_0_init_gart_aperture_regs()
68 if (adev->gmc.pdb0_bo) { in gfxhub_v1_0_init_gart_aperture_regs()
70 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
72 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
75 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
85 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
[all …]
H A Dgfxhub_v1_2.c78 adev->gmc.vram_start : adev->gmc.fb_start; in gfxhub_v1_2_xcc_init_gart_aperture_regs()
82 if (adev->gmc.pdb0_bo) in gfxhub_v1_2_xcc_init_gart_aperture_regs()
83 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
93 if (adev->gmc.pdb0_bo) { in gfxhub_v1_2_xcc_init_gart_aperture_regs()
103 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
106 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
110 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
113 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
117 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
120 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
[all …]
H A Dgmc_v6_0.c38 #include "gmc/gmc_6_0_d.h"
39 #include "gmc/gmc_6_0_sh_mask.h"
134 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v6_0_init_microcode()
140 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v6_0_init_microcode()
153 if (!adev->gmc.fw) in gmc_v6_0_mc_load_microcode()
156 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v6_0_mc_load_microcode()
160 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v6_0_mc_load_microcode()
163 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
166 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
257 adev->gmc in gmc_v6_0_mc_program()
[all...]
H A Dgfxhub_v1_1.c88 if (max_region || adev->gmc.xgmi.connected_to_cpu) { in gfxhub_v1_1_get_xgmi_info()
89 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in gfxhub_v1_1_get_xgmi_info()
91 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in gfxhub_v1_1_get_xgmi_info()
95 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
99 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
104 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in gfxhub_v1_1_get_xgmi_info()
107 adev->gmc.xgmi.node_segment_size = seg_size; in gfxhub_v1_1_get_xgmi_info()
H A Dmmhub_v4_2_0.c84 if (!adev->gmc.xgmi.connected_to_cpu) in mmhub_v4_2_0_get_xgmi_info()
98 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in mmhub_v4_2_0_get_xgmi_info()
100 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in mmhub_v4_2_0_get_xgmi_info()
103 adev->gmc.xgmi.physical_node_id = in mmhub_v4_2_0_get_xgmi_info()
106 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in mmhub_v4_2_0_get_xgmi_info()
109 adev->gmc.xgmi.node_segment_size = seg_size; in mmhub_v4_2_0_get_xgmi_info()
176 if (adev->gmc.pdb0_bo) in mmhub_v4_2_0_mid_init_gart_aperture_regs()
177 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
184 if (adev->gmc.pdb0_bo) { in mmhub_v4_2_0_mid_init_gart_aperture_regs()
187 (u32)(adev->gmc in mmhub_v4_2_0_mid_init_gart_aperture_regs()
[all...]
H A Dgfxhub_v12_1.c99 if (adev->gmc.pdb0_bo) in gfxhub_v12_1_xcc_init_gart_aperture_regs()
100 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
110 if (adev->gmc.pdb0_bo) { in gfxhub_v12_1_xcc_init_gart_aperture_regs()
113 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
116 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
120 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
123 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
127 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
130 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
134 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
[all …]
H A Dmmhub_v1_0.c48 adev->gmc.fb_start = base; in mmhub_v1_0_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_0_get_fb_location()
75 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v1_0_init_system_aperture_regs()
109 max((adev->gmc.fb_end >> 18) + 0x1, in mmhub_v1_0_init_system_aperture_regs()
[all …]
H A Damdgpu_gmc.h373 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
374 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
375 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
377 ((adev)->gmc.gmc_funcs->get_vm_pte((adev), (vm), (bo), (vm_flags), \
380 (adev)->gmc.gmc_funcs->override_vm_pte_flags \
382 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
385 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \
396 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) in amdgpu_gmc_vram_full_visible()
398 WARN_ON(gmc->real_vram_size < gmc in amdgpu_gmc_vram_full_visible()
394 amdgpu_gmc_vram_full_visible(struct amdgpu_gmc * gmc) amdgpu_gmc_vram_full_visible() argument
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H A Dgfxhub_v12_0.c148 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
153 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
164 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v12_0_init_system_aperture_regs()
165 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v12_0_init_system_aperture_regs()
169 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
171 max(adev->gmc.fb_end, adev->gmc in gfxhub_v12_0_init_system_aperture_regs()
[all...]
H A Dgfxhub_v3_0.c140 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc in gfxhub_v3_0_init_system_aperture_regs()
[all...]
H A Dgfxhub_v11_5_0.c145 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
168 max(adev->gmc.fb_end, adev->gmc in gfxhub_v11_5_0_init_system_aperture_regs()
[all...]
H A Dgfxhub_v2_0.c141 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
143 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs()
163 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
233 if (adev->gmc.translate_further) { in gfxhub_v2_0_init_cache_regs()
314 !adev->gmc.noretry); in gfxhub_v2_0_setup_vmid_config()
H A Dmmhub_v2_3.c131 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
133 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
136 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
138 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
148 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_3_init_system_aperture_regs()
149 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_3_init_system_aperture_regs()
153 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_3_init_system_aperture_regs()
155 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_3_init_system_aperture_regs()
219 if (adev->gmc.translate_further) { in mmhub_v2_3_init_cache_regs()
304 !adev->gmc.noretry); in mmhub_v2_3_setup_vmid_config()
[all …]
H A Dgfxhub_v3_0_3.c143 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
167 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
169 max(adev->gmc.fb_end, adev->gmc in gfxhub_v3_0_3_init_system_aperture_regs()
[all...]
H A Damdgpu_ttm.c138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && in amdgpu_evict_flags()
150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; in amdgpu_evict_flags()
237 *addr = amdgpu_compute_gart_address(&adev->gmc, entity, window); in amdgpu_ttm_map_buffer()
474 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size) in amdgpu_res_cpu_visible()
641 mem->bus.offset += adev->gmc.aper_base; in amdgpu_ttm_io_mem_reserve()
676 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; in amdgpu_ttm_io_mem_pfn()
692 return adev->gmc.gart_start; in amdgpu_ttm_domain_start()
694 return adev->gmc.vram_start; in amdgpu_ttm_domain_start()
992 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; in amdgpu_ttm_alloc_gart()
1178 if (adev->gmc in amdgpu_ttm_tt_create()
[all...]
H A Dmmhub_v3_0_2.c149 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
154 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
156 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
166 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
177 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
179 max(adev->gmc.fb_end, adev->gmc in mmhub_v3_0_2_init_system_aperture_regs()
[all...]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c82 unsigned int *gmc, in loongson_gfxpll_get_rates() argument
110 if (gmc) in loongson_gfxpll_get_rates()
111 *gmc = gmc_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()

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