Searched refs:dummy_pstate_latency_us (Results 1 – 6 of 6) sorted by relevance
247 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()249 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn32_build_wm_range_table_fpu()251 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn32_build_wm_range_table_fpu()253 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; in dcn32_build_wm_range_table_fpu()258 …l_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; in dcn32_build_wm_range_table_fpu()292 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()2304 …ncy_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { in dcn32_calculate_wm_and_dlg_fpu()2307 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()2352 …ncy_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { in dcn32_calculate_wm_and_dlg_fpu()2355 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()[all …]
236 double dummy_pstate_latency_us; member
359 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
296 .dummy_pstate_latency_us = 10.0472 …ext->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; in dcn315_update_soc_for_wm_a()
323 .dummy_pstate_latency_us = 5.0,434 .dummy_pstate_latency_us = 5.0,2021 if ((int)(bb->dummy_pstate_latency_us * 1000) in dcn20_patch_bounding_box()2024 bb->dummy_pstate_latency_us = in dcn20_patch_bounding_box()2105 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || in dcn20_validate_bandwidth_fp()2112 …ext->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; in dcn20_validate_bandwidth_fp()
200 …te_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us; in calculate_lowest_supported_state_for_temp_read()