| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp_cm.c | 51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block()
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
122 dpp1_power_on_degamma_lut(dpp_base, true); in dpp2_set_degamma_pwl()
123 dpp2_enable_cm_block(dpp_base); in dpp2_set_degamma_pwl()
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| H A D | dcn20_dpp.c | 51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
78 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
98 struct dpp *dpp_base, in dpp2_cnv_setup() argument
105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
244 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); in dpp2_cnv_setup()
246 dpp2_program_input_csc(dpp_base, color_space, select, NULL); in dpp2_cnv_setup()
255 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_cm.c | 161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap()
233 void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, in dpp1_cm_get_gamut_remap() argument
236 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_get_gamut_remap()
308 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
311 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default()
378 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
381 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment()
386 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut() argument
389 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut()
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| H A D | dcn10_dpp_dscl.c | 124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl() argument
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl()
613 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
619 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
630 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_dscl_set_scaler_manual_scale()
632 dpp1_power_on_dscl(dpp_base, true); in dpp1_dscl_set_scaler_manual_scale()
659 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) in dpp1_dscl_set_scaler_manual_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp_cm.c | 44 struct dpp *dpp_base) in dpp3_enable_cm_block() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block()
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current() argument
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current()
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut() argument
84 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut()
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() argument
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_gamcor_lut()
132 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { in dpp3_power_on_gamcor_lut()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
| H A D | dcn35_dpp.h | 53 struct dpp *dpp_base,
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 45 struct dpp *dpp_base, in dpp201_cnv_setup() argument
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup()
177 dpp1_program_input_csc(dpp_base, color_space, select, NULL); in dpp201_cnv_setup()
185 dpp2_power_on_obuf(dpp_base, true); in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 1072 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut() local
1081 &dpp_base->regamma_params, false); in dcn20_set_blend_lut()
1082 blend_lut = &dpp_base->regamma_params; in dcn20_set_blend_lut()
1084 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn20_set_blend_lut()
1092 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut() local
1101 &dpp_base->shaper_params, true); in dcn20_set_shaper_3dlut()
1102 shaper_lut = &dpp_base->shaper_params; in dcn20_set_shaper_3dlut()
1105 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); in dcn20_set_shaper_3dlut()
1107 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, in dcn20_set_shaper_3dlut()
1110 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); in dcn20_set_shaper_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 407 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts() local
435 &dpp_base->regamma_params, false); in dcn401_populate_mcm_luts()
436 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; in dcn401_populate_mcm_luts()
455 &dpp_base->regamma_params, true); in dcn401_populate_mcm_luts()
456 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; in dcn401_populate_mcm_luts()
611 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts() local
631 &dpp_base->regamma_params, false); in dcn401_set_mcm_luts()
632 lut_params = rval ? &dpp_base->regamma_params : NULL; in dcn401_set_mcm_luts()
643 &dpp_base->shaper_params, true); in dcn401_set_mcm_luts()
644 lut_params = rval ? &dpp_base->shaper_params : NULL; in dcn401_set_mcm_luts()
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