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Searched refs:display_cfg (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c157 static void get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in get_stream_output_bpp() argument
159 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in get_stream_output_bpp()
160 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in get_stream_output_bpp()
161 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in get_stream_output_bpp()
162 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in get_stream_output_bpp()
177 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in get_stream_output_bpp()
178 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in get_stream_output_bpp()
183 …_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in get_stream_output_bpp()
245 static bool dml_get_is_phantom_pipe(const struct dml2_display_cfg *display_cfg, const struct dml2_c… in dml_get_is_phantom_pipe() argument
249 bool is_phantom = dml_is_phantom_pipe(&display_cfg->plane_descriptors[plane_idx]); in dml_get_is_phantom_pipe()
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H A Ddml2_core_utils.c337 … dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in dml2_core_utils_get_stream_output_bpp() argument
339 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in dml2_core_utils_get_stream_output_bpp()
340 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
342 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in dml2_core_utils_get_stream_output_bpp()
357 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
358 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
364 …_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in dml2_core_utils_get_stream_output_bpp()
610 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,… in dml2_core_utils_expand_implict_subvp() argument
618 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
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H A Ddml2_core_dcn4.c303 static void expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct d… in expand_implict_subvp() argument
311 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in expand_implict_subvp()
316 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp()
320 if (!display_cfg->stage3.performed) { in expand_implict_subvp()
325 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in expand_implict_subvp()
326 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp()
330 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in expand_implict_subvp()
333 main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); in expand_implict_subvp()
345 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in expand_implict_subvp()
346 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in expand_implict_subvp()
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H A Ddml2_core_utils.h18 …dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
32 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,…
H A Ddml2_core_shared_types.h1313 const struct dml2_display_cfg *display_cfg; member
1439 const struct dml2_display_cfg *display_cfg; member
1665 const struct dml2_display_cfg *display_cfg; member
1719 const struct dml2_display_cfg *display_cfg; member
1773 const struct dml2_display_cfg *display_cfg; member
1864 const struct dml2_display_cfg *display_cfg; member
1921 const struct dml2_display_cfg *display_cfg; member
2210 const struct dml2_display_cfg *display_cfg; member
2243 const struct dml2_display_cfg *display_cfg; member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c39 if (in_out->display_cfg->stage3.success) in get_minimum_clocks_for_latency()
40 min_clock_index_for_latency = in_out->display_cfg->stage3.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
42 min_clock_index_for_latency = in_out->display_cfg->stage1.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
64 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_system_active_minimums()
70 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
111 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_svp_prefetch_minimums()
186 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_idle_minimums()
322 static bool map_soc_min_clocks_to_dpm_fine_grained(struct dml2_display_cfg_programming *display_cfg… in map_soc_min_clocks_to_dpm_fine_grained() argument
326 …result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.dcfclk_khz, &state_table->dcfc… in map_soc_min_clocks_to_dpm_fine_grained()
328 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn4_fams2.c235 static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int … in count_planes_with_stream_index() argument
240 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
241 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
1249 static bool all_planes_match_method(const struct display_configuation_with_meta *display_cfg, int p… in all_planes_match_method() argument
1255 …if (display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != dml2… in all_planes_match_method()
1256 …display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != pstate_m… in all_planes_match_method()
1318 const struct display_configuation_with_meta *display_cfg, in is_timing_group_schedulable() argument
1330 …for (base_stream_idx = 0; base_stream_idx < display_cfg->display_config.num_streams; base_stream_i… in is_timing_group_schedulable()
1345 for (i = base_stream_idx + 1; i < display_cfg->display_config.num_streams; i++) { in is_timing_group_schedulable()
1378 const struct display_configuation_with_meta *display_cfg, in is_config_schedulable() argument
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H A Ddml2_pmo_dcn4_fams2.h13 const struct display_configuation_with_meta *display_cfg,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/
H A Ddml2_top_soc15.c80 …l->test_mcache.validate_admissibility_params.display_cfg = &params->display_config->display_config; in dml2_top_optimization_test_function_mcache()
251 l->mode_support_params.display_cfg = &l->next_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase()
303 l->mode_support_params.display_cfg = &l->cur_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase_1()
533 for (plane_index = 0; plane_index < params->display_cfg->num_planes; plane_index++) { in dml2_top_mcache_validate_admissability()
534 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
537 plane = &params->display_cfg->plane_descriptors[plane_index]; in dml2_top_mcache_validate_admissability()
538 stream = &params->display_cfg->stream_descriptors[plane->stream_index]; in dml2_top_mcache_validate_admissability()
790 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
813 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
845 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c98 const struct dml_display_cfg_st *display_cfg, in pack_and_call_dml_mode_support_ex() argument
105 s->mode_support_params.in_display_cfg = display_cfg; in pack_and_call_dml_mode_support_ex()
238 static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, in are_timings_requiring_odm_doing_blending() argument
244 for (i = 0; i < display_cfg->num_surfaces; i++) in are_timings_requiring_odm_doing_blending()
245 planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; in are_timings_requiring_odm_doing_blending()
255 …figuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, in does_configuration_meet_sw_policies() argument
261 if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) in does_configuration_meet_sw_policies()
H A Ddisplay_mode_util.c742 dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_planes() argument
747 if (display_cfg->plane.ViewportWidth[k] > 0) in dml_get_num_active_planes()
757 dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_pipes() argument
761 for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) { in dml_get_num_active_pipes()
762 num_active_pipes = num_active_pipes + display_cfg->hw.DPPPerSurface[j]; in dml_get_num_active_pipes()
H A Ddisplay_mode_core.c372 …lockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t pto…
2704 …lockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t pto… in PixelClockAdjustmentForProgressiveToInterlaceUnit() argument
2706 dml_uint_t num_active_planes = dml_get_num_active_planes(display_cfg); in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2710 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2711 if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) { in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2712 display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
10090 const struct dml_display_cfg_st *display_cfg) in cache_display_cfg() argument
10092 mode_lib->ms.cache_display_cfg = *display_cfg; in cache_display_cfg()
10118 const struct dml_display_cfg_st *display_cfg) in dml_mode_support() argument
10124 cache_display_cfg(mode_lib, display_cfg); in dml_mode_support()
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/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c3441 const struct amd_pp_display_configuration *display_cfg = in si_apply_state_adjust_rules() local
3495 for (i = 0; i < display_cfg->num_display; i++) { in si_apply_state_adjust_rules()
3497 if (display_cfg->displays[i].pixel_clock > 297000) in si_apply_state_adjust_rules()
3678 display_cfg->display_clk, in si_apply_state_adjust_rules()