Home
last modified time | relevance | path

Searched refs:dccg_dcn (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto() local
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq() local
102 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_set_fifo_errdet_ovr_en() local
111 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_otg_add_pixel() local
123 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_otg_drop_pixel() local
134 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_init() local
150 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_refclk_setup() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.c34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
64 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg301_create() local
67 if (dccg_dcn == NULL) { in dccg301_create()
72 base = &dccg_dcn->base; in dccg301_create()
76 dccg_dcn->regs = regs; in dccg301_create()
77 dccg_dcn->dccg_shift = dccg_shift; in dccg301_create()
78 dccg_dcn->dccg_mask = dccg_mask; in dccg301_create()
80 return &dccg_dcn->base; in dccg301_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto() local
116 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_init() local
149 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg21_create() local
152 if (dccg_dcn == NULL) { in dccg21_create()
157 base = &dccg_dcn->base; in dccg21_create()
161 dccg_dcn->regs = regs; in dccg21_create()
162 dccg_dcn->dccg_shift = dccg_shift; in dccg21_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/
H A Ddcn201_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
73 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg201_create() local
76 if (dccg_dcn == NULL) { in dccg201_create()
81 base = &dccg_dcn->base; in dccg201_create()
85 dccg_dcn->regs = regs; in dccg201_create()
86 dccg_dcn->dccg_shift = dccg_shift; in dccg201_create()
87 dccg_dcn->dccg_mask = dccg_mask; in dccg201_create()
89 return &dccg_dcn->base; in dccg201_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn60/
H A Ddcn60_dccg.c14 (dccg_dcn->regs->reg)
18 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
21 dccg_dcn->base.ctx
32 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg60_set_pixel_rate_div() local
75 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg60_set_dto_dscclk() local
170 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg60_create() local
173 if (dccg_dcn == NULL) { in dccg60_create()
178 base = &dccg_dcn->base; in dccg60_create()
182 dccg_dcn->regs = regs; in dccg60_create()
183 dccg_dcn->dccg_shift = dccg_shift; in dccg60_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn42/
H A Ddcn42_dccg.c15 (dccg_dcn->regs->reg)
19 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
22 dccg_dcn->base.ctx
29 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_otg_add_pixel() local
56 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_otg_drop_pixel() local
82 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_enable_global_fgcg() local
95 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_get_global_fgcg_status() local
108 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_set_physymclk() local
199 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_disable_hdmistreamclk() local
212 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_disable_hdmicharclk() local
[all …]