Searched refs:dc_balance (Results 1 – 4 of 4) sorted by relevance
379 crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax; in intel_vrr_dc_balance_compute_config()380 crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin; in intel_vrr_dc_balance_compute_config()381 crtc_state->vrr.dc_balance.max_increase = in intel_vrr_dc_balance_compute_config()383 crtc_state->vrr.dc_balance.max_decrease = in intel_vrr_dc_balance_compute_config()385 crtc_state->vrr.dc_balance.guardband = in intel_vrr_dc_balance_compute_config()386 DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax * in intel_vrr_dc_balance_compute_config()390 crtc_state->vrr.dc_balance.guardband); in intel_vrr_dc_balance_compute_config()397 crtc_state->vrr.dc_balance.slope = in intel_vrr_dc_balance_compute_config()399 crtc_state->vrr.dc_balance.vblank_target = in intel_vrr_dc_balance_compute_config()402 crtc_state->vrr.dc_balance.enable = true; in intel_vrr_dc_balance_compute_config()[all …]
1395 } dc_balance; member1538 } dc_balance; member
5478 PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); in intel_pipe_config_compare()5479 PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); in intel_pipe_config_compare()5480 PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); in intel_pipe_config_compare()5481 PIPE_CONF_CHECK_I(vrr.dc_balance.slope); in intel_pipe_config_compare()5482 PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); in intel_pipe_config_compare()5483 PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); in intel_pipe_config_compare()5484 PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); in intel_pipe_config_compare()6865 if (new_crtc_state->vrr.dc_balance.enable) in intel_update_crtc()7330 if (new_crtc_state->vrr.dc_balance.enable) { in intel_atomic_dsb_finish()7399 if (new_crtc_state->vrr.dc_balance.enable) in intel_atomic_dsb_finish()
707 if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) { in intel_dsb_vblank_evade()