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Searched refs:clk_pre (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c123 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc()
126 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc()
136 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc()
237 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v2()
240 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v2()
250 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v2()
345 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v3()
348 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v3()
360 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v3()
457 timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin; in msm_dsi_dphy_timing_calc_v4()
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H A Ddsi_phy_7nm.c1035 writel(timing->shared_timings.clk_pre, in dsi_7nm_phy_enable()
1057 writel(timing->shared_timings.clk_pre, in dsi_7nm_phy_enable()
/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
123 if (cfg->clk_pre < 8) in phy_mipi_dphy_config_validate()
/linux/include/linux/phy/
H A Dphy-mipi-dphy.h47 unsigned int clk_pre; member
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c372 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; in inno_dsidphy_mipi_mode_enable() local
435 clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); in inno_dsidphy_mipi_mode_enable()
508 T_CLK_PRE_CNT(clk_pre)); in inno_dsidphy_mipi_mode_enable()
/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi.h129 u32 clk_pre; member
H A Ddsi_host.c802 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); in dsi_ctrl_enable()
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c254 DIV_ROUND_UP(priv->config.clk_pre, BITS_PER_BYTE)); in phy_meson_axg_mipi_dphy_power_on()
/linux/drivers/gpu/drm/bridge/
H A Dnwl-dsi.c232 cycles = ui2bc(cfg->clk_pre); in nwl_dsi_config_host()
237 cycles += ui2bc(cfg->clk_pre); in nwl_dsi_config_host()