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Searched refs:clk_mgr_internal (Results 1 – 25 of 33) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h114 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
115 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
116 int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
117 int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
118 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
119 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
120 void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
121 void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
122 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
123 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h196 int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
197 int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
198 int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
199 int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
200 int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc…
201 int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
202 void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
203 void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
204 void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
205 void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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H A Ddcn35_clk_mgr.h45 struct clk_mgr_internal base;
61 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
H A Ddcn35_clk_mgr.c201 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_disable_otg_wa() local
202 struct dccg *dccg = clk_mgr_internal->dccg; in dcn35_disable_otg_wa()
256 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, in dcn35_update_clocks_update_dtb_dto()
294 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, in dcn35_update_clocks_update_dpp_dto()
359 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_notify_host_router_bw()
396 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_update_clocks()
552 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) in get_vco_frequency_from_reg()
584 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_enable_pme_wa()
611 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_save_clk_registers_internal()
725 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_is_spll_ssc_enabled()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h93 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
94 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
95 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
96 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
97 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
98 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
100 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
101 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
102 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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H A Ddcn314_smu.c101 static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn314_smu_wait_for_response()
119 static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn314_smu_send_msg_with_param()
166 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn314_smu_get_smu_version()
175 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn314_smu_set_dispclk()
191 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn314_smu_set_dprefclk()
208 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn314_smu_set_hard_min_dcfclk()
226 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf… in dcn314_smu_set_min_deep_sleep_dcfclk()
244 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn314_smu_set_dppclk()
259 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn314_smu_set_display_idle_optimization()
274 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn314_smu_enable_phy_refclk_pwrdwn()
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H A Ddcn314_clk_mgr.c179 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_is_spll_ssc_enabled()
189 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); in dcn314_init_clocks()
213 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_update_clocks()
340 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) in get_vco_frequency_from_reg()
372 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_enable_pme_wa()
556 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_notify_wm_ranges()
577 static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, in dcn314_get_dpm_table_from_smu()
630 static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr, in dcn314_clk_mgr_helper_populate_bw_params()
779 static void dcn314_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) in dcn314_read_ss_info_from_lut()
927 void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) in dcn314_clk_mgr_destroy()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h122 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
123 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
124 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
125 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
128 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
129 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
130 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
131 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
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H A Ddcn316_smu.c100 static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn316_smu_wait_for_response()
119 struct clk_mgr_internal *clk_mgr, in dcn316_smu_send_msg_with_param()
152 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn316_smu_get_smu_version()
161 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn316_smu_set_dispclk()
177 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn316_smu_set_hard_min_dcfclk()
195 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf… in dcn316_smu_set_min_deep_sleep_dcfclk()
213 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn316_smu_set_dppclk()
228 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn316_smu_set_display_idle_optimization()
243 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn316_smu_enable_phy_refclk_pwrdwn()
261 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) in dcn316_smu_set_dram_addr_high()
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H A Ddcn316_clk_mgr.h38 struct clk_mgr_internal base;
47 void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h150 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
151 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
152 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
153 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
154 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
157 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
158 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
159 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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H A Ddcn301_smu.c80 static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn301_smu_wait_for_response()
98 static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn301_smu_send_msg_with_param()
133 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn301_smu_get_smu_version()
145 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn301_smu_set_dispclk()
160 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn301_smu_set_dprefclk()
176 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn301_smu_set_hard_min_dcfclk()
190 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf… in dcn301_smu_set_min_deep_sleep_dcfclk()
204 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn301_smu_set_dppclk()
218 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn301_smu_set_display_idle_optimization()
230 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn301_smu_enable_phy_refclk_pwrdwn()
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H A Dvg_clk_mgr.h41 struct clk_mgr_internal base;
50 void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c85 static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn31_smu_wait_for_response()
103 static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn31_smu_send_msg_with_param()
147 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn31_smu_get_smu_version()
156 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn31_smu_set_dispclk()
172 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn31_smu_set_dprefclk()
189 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn31_smu_set_hard_min_dcfclk()
207 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc… in dcn31_smu_set_min_deep_sleep_dcfclk()
225 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn31_smu_set_dppclk()
240 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn31_smu_set_display_idle_optimization()
255 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn31_smu_enable_phy_refclk_pwrdwn()
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H A Ddcn31_smu.h254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
257 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
258 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc…
259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
263 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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H A Ddcn31_clk_mgr.h38 struct clk_mgr_internal base;
56 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
H A Ddcn31_clk_mgr.c142 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn31_update_clocks()
261 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) in get_vco_frequency_from_reg()
293 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn31_enable_pme_wa()
485 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn31_notify_wm_ranges()
506 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, in dcn31_get_dpm_table_from_smu()
562 static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr, in dcn31_clk_mgr_helper_populate_bw_params()
643 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn31_set_low_power_state()
810 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) in dcn31_clk_mgr_destroy()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr_smu_msg.h39 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
40 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
41 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
42 void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
43 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_…
44 void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
H A Ddcn32_clk_mgr.h31 struct clk_mgr_internal *clk_mgr,
35 void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
38 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.h32 struct clk_mgr_internal *clk_mgr);
36 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);
37 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.h36 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
42 struct clk_mgr_internal *clk_mgr,
53 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30m_clk_mgr_smu_msg.c53 static uint32_t dcn30m_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, in dcn30m_smu_wait_for_response()
76 static bool dcn30m_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn30m_smu_send_msg_with_param()
108 uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set) in dcn30m_smu_set_smart_mux_switch()
H A Ddcn30m_clk_mgr_smu_msg.h31 struct clk_mgr_internal;
33 uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set…
H A Ddcn30_clk_mgr.h92 struct clk_mgr_internal *clk_mgr,
96 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.h29 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);
30 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);

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