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Searched refs:clk_mgr_base (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/
H A Ddcn42_clk_mgr.c114 static uint32_t dcn42_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock) in dcn42_get_clock_freq_from_clkip() argument
116 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn42_get_clock_freq_from_clkip()
211 void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, in dcn42_update_clocks() argument
216 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn42_update_clocks()
218 struct dc *dc = clk_mgr_base->ctx->dc; in dcn42_update_clocks()
237 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn42_update_clocks()
239 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn42_update_clocks()
242 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn42_update_clocks()
245 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn42_update_clocks()
248 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn42_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c84 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, in dcn201_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn201_update_clocks()
90 struct dc *dc = clk_mgr_base->ctx->dc; in dcn201_update_clocks()
101 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
113 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn201_update_clocks()
116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
117 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
124 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
127 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) in dcn201_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c216 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, in dcn2_update_clocks() argument
220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn2_update_clocks()
222 struct dc *dc = clk_mgr_base->ctx->dc; in dcn2_update_clocks()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
242 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
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H A Ddcn20_clk_mgr.h56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c187 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, in rv1_update_clocks() argument
191 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_update_clocks()
192 struct dc *dc = clk_mgr_base->ctx->dc; in rv1_update_clocks()
224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
225 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
227 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) in rv1_update_clocks()
230 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
231 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks()
239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_update_clocks()
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
109 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
117 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
119 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.c70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock() argument
72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock()
74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce112_set_clock()
75 struct dc *dc = clk_mgr_base->ctx->dc; in dce112_set_clock()
104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && in dce112_set_clock()
105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) in dce112_set_clock()
191 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, in dce112_update_clocks() argument
195 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks()
203 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce112_update_clocks()
207 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce112_update_clocks()
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H A Ddce112_clk_mgr.h35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.h34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
36 struct clk_mgr *clk_mgr_base,
51 struct clk_mgr *clk_mgr_base,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.h107 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);
108 bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);
115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/
H A Dclk_mgr.c388 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) in dc_destroy_clk_mgr() argument
390 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr()
393 switch (clk_mgr_base->ctx->asic_id.chip_family) { in dc_destroy_clk_mgr()
395 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
397 } else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
400 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
406 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) in dc_destroy_clk_mgr()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30m_clk_mgr.c31 uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set) in dcn30m_set_smartmux_switch() argument
33 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn30m_set_smartmux_switch()
H A Ddcn30m_clk_mgr.h29 uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set);
H A Ddcn30_clk_mgr.h89 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.h45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.h52 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
68 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.h28 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);