Searched refs:clk_divider (Results 1 – 2 of 2) sorted by relevance
1194 uint32_t clk_divider, reg; in sdhci_fsl_fdt_tune() local1211 clk_divider = sc->baseclk_hz / slot->clock; in sdhci_fsl_fdt_tune()1212 if (clk_divider < 3 || clk_divider > 16) in sdhci_fsl_fdt_tune()
1841 uint8_t clk_divider, n, div, mcu; local1857 clk_divider = RTSX_CLK_DIVIDE_128;1860 clk_divider = RTSX_CLK_DIVIDE_0;1862 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider);