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Searched refs:cfg_val (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_gamma.c121 u32 cfg_val, data_mode, lbank_val, word[2]; in mtk_gamma_set() local
190 cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); in mtk_gamma_set()
195 cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1); in mtk_gamma_set()
197 cfg_val &= ~GAMMA_LUT_TYPE; in mtk_gamma_set()
201 cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); in mtk_gamma_set()
204 cfg_val &= ~GAMMA_RELAY_MODE; in mtk_gamma_set()
206 writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); in mtk_gamma_set()
H A Dmtk_disp_aal.c101 u32 cfg_val; in mtk_aal_gamma_set() local
126 cfg_val = readl(aal->regs + DISP_AAL_CFG); in mtk_aal_gamma_set()
129 cfg_val |= FIELD_PREP(AAL_GAMMA_LUT_EN, 1); in mtk_aal_gamma_set()
132 cfg_val &= ~AAL_RELAY_MODE; in mtk_aal_gamma_set()
134 writel(cfg_val, aal->regs + DISP_AAL_CFG); in mtk_aal_gamma_set()
/linux/sound/x86/
H A Dintel_hdmi_audio.c354 union aud_cfg cfg_val = {.regval = 0}; in had_init_audio_ctrl() local
366 cfg_val.regx.num_ch = channels - 2; in had_init_audio_ctrl()
368 cfg_val.regx.layout = LAYOUT0; in had_init_audio_ctrl()
370 cfg_val.regx.layout = LAYOUT1; in had_init_audio_ctrl()
373 cfg_val.regx.packet_mode = 1; in had_init_audio_ctrl()
376 cfg_val.regx.left_align = 1; in had_init_audio_ctrl()
378 cfg_val.regx.val_bit = 1; in had_init_audio_ctrl()
382 cfg_val.regx.dp_modei = 1; in had_init_audio_ctrl()
383 cfg_val.regx.set = 1; in had_init_audio_ctrl()
386 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); in had_init_audio_ctrl()
[all …]
/linux/drivers/pinctrl/bcm/
H A Dpinctrl-bcm281xx.c1331 u32 cfg_val, cfg_mask; in bcm281xx_pinctrl_pin_config_set() local
1334 cfg_val = 0; in bcm281xx_pinctrl_pin_config_set()
1342 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1347 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1352 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1367 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1369 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); in bcm281xx_pinctrl_pin_config_set()
/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c290 u32 cfg_val; in xvcu_pll_set_div() local
301 cfg_val = FIELD_PREP(VCU_PLL_CFG_RES, cfg->res) | in xvcu_pll_set_div()
306 xvcu_write(base, VCU_PLL_CFG, cfg_val); in xvcu_pll_set_div()
/linux/drivers/media/i2c/
H A Dtc358746.c464 static u32 tc358746_cfg_to_cnt(unsigned int cfg_val, in tc358746_cfg_to_cnt() argument
468 return DIV_ROUND_UP(cfg_val * clk_mhz, time_base); in tc358746_cfg_to_cnt()
471 static u32 tc358746_ps_to_cnt(unsigned int cfg_val, in tc358746_ps_to_cnt() argument
474 return tc358746_cfg_to_cnt(cfg_val, clk_mhz, USEC_PER_SEC); in tc358746_ps_to_cnt()
477 static u32 tc358746_us_to_cnt(unsigned int cfg_val, in tc358746_us_to_cnt() argument
480 return tc358746_cfg_to_cnt(cfg_val, clk_mhz, 1); in tc358746_us_to_cnt()
/linux/include/linux/
H A Dresctrl.h259 u32 closid, enum resctrl_conf_type t, u32 cfg_val);
/linux/drivers/tty/serial/8250/
H A D8250_exar.c848 u16 cfg_val; in cti_board_init_fpga() local
854 ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val); in cti_board_init_fpga()
858 cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT; in cti_board_init_fpga()
859 ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val); in cti_board_init_fpga()
/linux/arch/x86/kernel/cpu/resctrl/
H A Dctrlmondata.c281 u32 closid, enum resctrl_conf_type t, u32 cfg_val) in resctrl_arch_update_one() argument
291 hw_dom->ctrl_val[idx] = cfg_val; in resctrl_arch_update_one()
/linux/arch/loongarch/kernel/
H A Dptrace.c234 u32 cfg_val; in cfg_get() local
238 cfg_val = read_cpucfg(i++); in cfg_get()
239 r = membuf_write(&to, &cfg_val, sizeof(u32)); in cfg_get()
/linux/drivers/misc/cardreader/
H A Drtsx_pcr.c1366 u16 cfg_val; in rtsx_pci_init_chip() local
1440 pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val); in rtsx_pci_init_chip()
1441 if (cfg_val & PCI_EXP_LNKCTL_ASPM_L1) in rtsx_pci_init_chip()
1478 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val); in rtsx_pci_init_chip()
1479 if (cfg_val & PCI_EXP_DEVCTL2_LTR_EN) { in rtsx_pci_init_chip()
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c9291 u32 cfg_val; in tg3_chip_reset() local
9297 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9299 cfg_val | (1 << 15)); in tg3_chip_reset()