Searched refs:cfg_off (Results 1 – 4 of 4) sorted by relevance
68 u32 cfg_off; member122 mask = PRIO_MASK << qos->cfg_off; in imx93_blk_ctrl_set_qos()123 mask |= PRIO_MASK << (qos->cfg_off + 4); in imx93_blk_ctrl_set_qos()124 val = qos->cfg_prio << qos->cfg_off; in imx93_blk_ctrl_set_qos()125 val |= qos->default_prio << (qos->cfg_off + 4); in imx93_blk_ctrl_set_qos()395 .cfg_off = PXP_R_CFG_QOS_OFF,400 .cfg_off = PXP_W_CFG_QOS_OFF,417 .cfg_off = LCDIF_CFG_QOS_OFF,434 .cfg_off = ISI_Y_W_CFG_QOS_OFF,439 .cfg_off = ISI_Y_R_CFG_QOS_OFF,[all …]
49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)50 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)51 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)52 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
657 .cfg_off = 0x20,
2021 u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW - in goya_init_tpc_qmans() local2032 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off, in goya_init_tpc_qmans()2034 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off, in goya_init_tpc_qmans()