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Searched refs:cfg_mask (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/armada/
H A Darmada_plane.c141 u32 cfg, cfg_mask, val; in armada_drm_primary_plane_atomic_update() local
196 cfg_mask = CFG_GRAFORMAT | in armada_drm_primary_plane_atomic_update()
203 cfg_mask = CFG_GRA_ENA; in armada_drm_primary_plane_atomic_update()
205 cfg = cfg_mask = 0; in armada_drm_primary_plane_atomic_update()
209 cfg_mask |= CFG_GRA_HSMOOTH; in armada_drm_primary_plane_atomic_update()
215 if (cfg_mask) in armada_drm_primary_plane_atomic_update()
216 armada_reg_queue_mod(regs, idx, cfg, cfg_mask, in armada_drm_primary_plane_atomic_update()
H A Darmada_overlay.c81 u32 cfg, cfg_mask, val; in armada_drm_overlay_plane_atomic_update() local
156 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT | in armada_drm_overlay_plane_atomic_update()
163 cfg_mask = CFG_DMA_ENA; in armada_drm_overlay_plane_atomic_update()
165 cfg = cfg_mask = 0; in armada_drm_overlay_plane_atomic_update()
169 cfg_mask |= CFG_DMA_HSMOOTH; in armada_drm_overlay_plane_atomic_update()
175 if (cfg_mask) in armada_drm_overlay_plane_atomic_update()
176 armada_reg_queue_mod(regs, idx, cfg, cfg_mask, in armada_drm_overlay_plane_atomic_update()
/linux/drivers/pinctrl/bcm/
H A Dpinctrl-bcm281xx.c2008 u32 cfg_val, cfg_mask; in bcm281xx_pinctrl_pin_config_set() local
2012 cfg_mask = 0; in bcm281xx_pinctrl_pin_config_set()
2019 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2025 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2028 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2033 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2048 __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2058 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); in bcm281xx_pinctrl_pin_config_set()
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_fw_funcs.c1388 u32 reg_val, cfg_mask; in qed_set_vxlan_no_l2_enable() local
1394 cfg_mask = BIT(PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET); in qed_set_vxlan_no_l2_enable()
1398 reg_val |= cfg_mask; in qed_set_vxlan_no_l2_enable()
1407 reg_val &= ~cfg_mask; in qed_set_vxlan_no_l2_enable()
/linux/drivers/net/wireless/realtek/rtw89/
H A Dphy.c208 u64 cfg_mask; in rtw89_phy_ra_mask_cfg() local
216 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, in rtw89_phy_ra_mask_cfg()
221 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, in rtw89_phy_ra_mask_cfg()
226 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, in rtw89_phy_ra_mask_cfg()
235 cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[0], in rtw89_phy_ra_mask_cfg()
237 cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[1], in rtw89_phy_ra_mask_cfg()
240 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], in rtw89_phy_ra_mask_cfg()
242 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], in rtw89_phy_ra_mask_cfg()
245 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], in rtw89_phy_ra_mask_cfg()
247 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], in rtw89_phy_ra_mask_cfg()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_common.c3957 u8 caps_mask, cfg_mask; in ice_phy_caps_equals_cfg() local
3967 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; in ice_phy_caps_equals_cfg()
3971 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || in ice_phy_caps_equals_cfg()