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Searched refs:bottom_pipe (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1581 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1584 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { in dcn30_split_stream_for_mpc_or_odm()
1585 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1586 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm()
1602 if (pri_pipe->bottom_pipe) { in dcn30_split_stream_for_mpc_or_odm()
1603 ASSERT(pri_pipe->bottom_pipe != sec_pipe); in dcn30_split_stream_for_mpc_or_odm()
1604 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; in dcn30_split_stream_for_mpc_or_odm()
1605 sec_pipe->bottom_pipe->top_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1607 pri_pipe->bottom_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1738 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; in dcn30_internal_validate_bw()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c570 pipe = pipe->bottom_pipe; in dcn32_get_num_free_pipes()
641 pipe = pipe->bottom_pipe; in dcn32_assign_subvp_pipe()
695 pipe = pipe->bottom_pipe; in dcn32_enough_pipes_for_subvp()
1864 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; in dcn32_split_stream_for_mpc_or_odm()
1867 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { in dcn32_split_stream_for_mpc_or_odm()
1868 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; in dcn32_split_stream_for_mpc_or_odm()
1869 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; in dcn32_split_stream_for_mpc_or_odm()
1886 if (pri_pipe->bottom_pipe) { in dcn32_split_stream_for_mpc_or_odm()
1887 ASSERT(pri_pipe->bottom_pipe != sec_pipe); in dcn32_split_stream_for_mpc_or_odm()
1888 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; in dcn32_split_stream_for_mpc_or_odm()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c1852 const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
1866 cur_sec_dpp = cur_sec_dpp->bottom_pipe; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
2057 pipe = pipe->bottom_pipe; in resource_get_dpp_pipes_for_opp_head()
2087 pipe = pipe->bottom_pipe; in resource_get_dpp_pipes_for_plane()
2142 const struct pipe_ctx *other_pipe = pipe->bottom_pipe; in resource_get_mpc_slice_count()
2146 other_pipe = other_pipe->bottom_pipe; in resource_get_mpc_slice_count()
2291 if (pipe_a->bottom_pipe && pipe_b->bottom_pipe) { in resource_is_pipe_topology_changed()
2292 if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx) in resource_is_pipe_topology_changed()
2294 if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) && in resource_is_pipe_topology_changed()
2295 (pipe_b->bottom_pipe->plane_state != pipe_b->plane_state)) in resource_is_pipe_topology_changed()
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H A Ddc_hw_sequencer.c898 current_mpc_pipe = current_mpc_pipe->bottom_pipe; in hwss_build_fast_sequence()
931 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe && in hwss_build_fast_sequence()
946 current_mpc_pipe = current_mpc_pipe->bottom_pipe; in hwss_build_fast_sequence()
2088 while (bottom_pipe_ctx->bottom_pipe != NULL) in get_surface_tile_visual_confirm_color()
2089 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; in get_surface_tile_visual_confirm_color()
H A Ddc.c4315 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) in commit_planes_for_stream()
4654 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe || in commit_planes_for_stream()
6979 if (pipe_ctx->bottom_pipe) { in dc_capture_register_software_state()
6980 state->mpc.mpcc_bot_sel[i] = pipe_ctx->bottom_pipe->pipe_idx; in dc_capture_register_software_state()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1539 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe; in dcn20_split_stream_for_odm()
1542 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) { in dcn20_split_stream_for_odm()
1543 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe; in dcn20_split_stream_for_odm()
1544 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe; in dcn20_split_stream_for_odm()
1578 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; in dcn20_split_stream_for_mpc()
1581 secondary_pipe->bottom_pipe = sec_bot_pipe; in dcn20_split_stream_for_mpc()
1591 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { in dcn20_split_stream_for_mpc()
1592 ASSERT(!secondary_pipe->bottom_pipe); in dcn20_split_stream_for_mpc()
1593 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; in dcn20_split_stream_for_mpc()
1594 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; in dcn20_split_stream_for_mpc()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_dc_resource_mgmt.c164 mpc_pipe = mpc_pipe->bottom_pipe; in find_pipes_assigned_to_plane()
582 …top_pipe->bottom_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]]; in add_plane_to_blend_tree()
587 state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].bottom_pipe = NULL; in add_plane_to_blend_tree()
740 pipe->top_pipe->bottom_pipe = pipe->bottom_pipe; in remove_pipes_from_blend_trees()
742 if (pipe->bottom_pipe) in remove_pipes_from_blend_trees()
743 pipe->bottom_pipe = pipe->top_pipe; in remove_pipes_from_blend_trees()
H A Ddml2_translation_helper.c1228 pipe = pipe->bottom_pipe; in dml2_populate_pipe_to_plane_index_mapping()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1719 curr_pipe = curr_pipe->bottom_pipe; in dcn32_enable_phantom_plane()
2748 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) in find_idle_secondary_pipe_check_mpo()
2749 && (!primary_pipe->bottom_pipe)) in find_idle_secondary_pipe_check_mpo()
2750 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; in find_idle_secondary_pipe_check_mpo()
2801 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2802 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2803 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c998 if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) { in dcn401_set_cursor_position()
1082 (pipe_ctx == pipe_ctx->top_pipe->bottom_pipe)) { in dcn401_set_cursor_position()
1280 pipe_ctx = pipe_ctx->bottom_pipe; in dcn401_wait_for_dcc_meta_propagation()
1826 for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { in dcn401_perform_3dlut_wa_unlock()
1951 pipe_ctx->bottom_pipe = NULL; in dcn401_reset_back_end_for_pipe()
2014 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { in dcn401_calculate_vready_offset_for_group()
2474 pipe = pipe->bottom_pipe; in dcn401_program_front_end_for_ctx()
2586 pipe = pipe->bottom_pipe; in dcn401_post_unlock_program_front_end()
3397 pipe_ctx->bottom_pipe = NULL; in dcn401_disable_plane_sequence()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1768 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw()
2701 if (pipe_ctx->bottom_pipe) { in program_surface_visibility()
2704 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); in program_surface_visibility()
2706 if (pipe_ctx->bottom_pipe->plane_state->visible) { in program_surface_visibility()
3062 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_program_front_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c856 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; in dcn21_fast_validate_bw()
880 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; in dcn21_fast_validate_bw()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c429 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; in dcn201_update_mpcc()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1593 …pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pi… in dcn20_populate_dml_pipes_from_context()
1657 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; in dcn20_populate_dml_pipes_from_context()
1661 split_pipe = split_pipe->bottom_pipe; in dcn20_populate_dml_pipes_from_context()