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Searched refs:bank (Results 1 – 25 of 519) sorted by relevance

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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c62 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
73 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
78 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
80 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
82 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
84 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
[all …]
H A Dpinctrl-samsung.c356 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument
368 if (bank) in pin_to_reg_bank()
369 *bank = b; in pin_to_reg_bank()
378 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local
390 pin_to_reg_bank(drvdata, grp->pins[0], &reg, &pin_offset, &bank); in samsung_pinmux_setup()
391 type = bank->type; in samsung_pinmux_setup()
406 raw_spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup()
413 raw_spin_unlock_irqrestore(&bank->slock, flags); in samsung_pinmux_setup()
442 struct samsung_pin_bank *bank; in samsung_pinconf_rw() local
451 pin_to_reg_bank(drvdata, pin, &reg_base, &pin_offset, &bank); in samsung_pinconf_rw()
[all …]
H A Dpinctrl-s3c64xx.c217 struct samsung_pin_bank *bank; member
281 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
283 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
291 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
302 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
306 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
309 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
318 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
319 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c64xx_gpio_irq_set_mask()
320 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask()
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.h37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
39 ADF_RING_BUNDLE_SIZE * (bank) + \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
43 ADF_RING_BUNDLE_SIZE * (bank) + \
45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
[all …]
H A Dadf_gen4_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_stat() argument
35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
[all …]
H A Dadf_transport.c40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
H A Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
[all …]
H A Dadf_gen2_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
[all …]
H A Dadf_accel_devices.h166 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
168 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
170 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
172 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
174 u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);
175 u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);
176 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
177 u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);
178 u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);
179 u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u32 bank);
[all …]
/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h442 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
443 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
444 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
446 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
447 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
448 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
449 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
451 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
452 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
453 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c184 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
219 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
222 bank->pin_backup[offset].value = value; in stm32_gpio_backup_value()
225 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
228 bank->pin_backup[offset].mode = mode; in stm32_gpio_backup_mode()
229 bank->pin_backup[offset].alt = alt; in stm32_gpio_backup_mode()
232 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
235 bank->pin_backup[offset].drive = drive; in stm32_gpio_backup_driving()
238 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_speed() argument
241 bank->pin_backup[offset].speed = speed; in stm32_gpio_backup_speed()
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
[all …]
/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh182 create_bank chip bank
184 test -n `cat $CONFIGFS_DIR/chip/bank/chip_name` || fail "chip_name doesn't work"
190 create_bank chip bank
197 create_bank chip bank
207 create_bank chip bank
215 create_bank chip bank
216 set_num_lines chip bank 16
224 create_bank chip bank
225 set_label chip bank foobar
233 create_bank chip bank
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/linux/drivers/bus/
H A Duniphier-system-bus.c35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
86 priv->bank[bank].base = paddr; in uniphier_system_bus_add_bank()
87 priv->bank[bank].end = end; in uniphier_system_bus_add_bank()
90 bank, priv->bank[bank].base, priv->bank[bank].end); in uniphier_system_bus_add_bank()
[all …]
/linux/arch/x86/kernel/cpu/mce/
H A Dintel.c138 static void cmci_set_threshold(int bank, int thresh) in cmci_set_threshold() argument
144 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
146 wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
150 void mce_intel_handle_storm(int bank, bool on) in mce_intel_handle_storm() argument
153 cmci_set_threshold(bank, CMCI_STORM_THRESHOLD); in mce_intel_handle_storm()
155 cmci_set_threshold(bank, cmci_threshold[bank]); in mce_intel_handle_storm()
176 static bool cmci_skip_bank(int bank, u64 *val) in cmci_skip_bank() argument
180 if (test_bit(bank, owned)) in cmci_skip_bank()
184 if (test_bit(bank, mce_banks_ce_disabled)) in cmci_skip_bank()
187 rdmsrq(MSR_IA32_MCx_CTL2(bank), *val); in cmci_skip_bank()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c900 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
903 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
910 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1276 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1279 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1286 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1301 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
1303 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1314 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1319 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
[all …]
H A Dpinctrl-microchip-sgpio.c354 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_get() local
356 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_get()
364 val = bank->is_input; in sgpio_pinconf_get()
368 val = !bank->is_input; in sgpio_pinconf_get()
372 if (bank->is_input) in sgpio_pinconf_get()
389 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_set() local
390 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_set()
403 if (bank->is_input) in sgpio_pinconf_set()
455 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_gpio_set_direction() local
457 return (input == bank->is_input) ? 0 : -EINVAL; in sgpio_gpio_set_direction()
[all …]
/linux/drivers/pinctrl/meson/
H A Dpinctrl-amlogic-a4.c224 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); in aml_pctl_set_function() local
228 unsigned int offset = bank->mux_bit_offs; in aml_pctl_set_function()
233 p_mux = bank->p_mux; in aml_pctl_set_function()
236 bank = NULL; in aml_pctl_set_function()
239 bank = &info->banks[i]; in aml_pctl_set_function()
244 if (!bank || !bank->reg_mux) in aml_pctl_set_function()
250 return regmap_update_bits(bank->reg_mux, reg, in aml_pctl_set_function()
258 if (!bank->reg_mux) in aml_pctl_set_function()
262 return regmap_update_bits(bank->reg_mux, reg, in aml_pctl_set_function()
332 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); in aml_calc_reg_and_bit() local
[all …]
/linux/sound/pci/au88x0/
H A Dau88x0_wt.h21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */ argument
22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */ argument
23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */ argument
24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */ argument
25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */ argument
26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */ argument
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi12 gpa0: gpa0-gpio-bank {
20 gpa1: gpa1-gpio-bank {
28 gpa2: gpa2-gpio-bank {
36 gpb0: gpb0-gpio-bank {
44 gpb1: gpb1-gpio-bank {
52 gpb2: gpb2-gpio-bank {
60 gpb3: gpb3-gpio-bank {
68 gpc0: gpc0-gpio-bank {
76 gpc3: gpc3-gpio-bank {
84 gpc1: gpc1-gpio-bank {
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sunxi.h37 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
38 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
229 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) in sunxi_irq_hw_bank_num() argument
232 return bank; in sunxi_irq_hw_bank_num()
234 return desc->irq_bank_map[bank]; in sunxi_irq_hw_bank_num()
240 u8 bank = irq / IRQ_PER_BANK; in sunxi_irq_cfg_reg() local
244 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; in sunxi_irq_cfg_reg()
253 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) in sunxi_irq_ctrl_reg_from_bank() argument
255 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; in sunxi_irq_ctrl_reg_from_bank()
261 u8 bank = irq / IRQ_PER_BANK; in sunxi_irq_ctrl_reg() local
[all …]
/linux/drivers/gpio/
H A Dgpio-f7188x.c96 struct f7188x_gpio_bank *bank; member
293 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get_direction() local
294 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get_direction()
302 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_get_direction()
318 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_direction_in() local
319 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_direction_in()
327 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_direction_in()
333 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir); in f7188x_gpio_direction_in()
343 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get() local
344 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get()
[all …]
H A Dgpio-mt7621.c34 int bank; member
65 struct mtk_gc *bank = gpiochip_get_data(gc); in mt7621_gpio_gc_to_priv() local
67 return bank->parent_priv; in mt7621_gpio_gc_to_priv()
84 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; in mtk_gpio_w32()
94 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; in mtk_gpio_r32()
99 mt7621_gpio_irq_bank_handler(struct mtk_gc *bank) in mt7621_gpio_irq_bank_handler() argument
101 struct mtk *priv = bank->parent_priv; in mt7621_gpio_irq_bank_handler()
103 int hwbase = bank->chip.gc.offset; in mt7621_gpio_irq_bank_handler()
107 pending = mtk_gpio_r32(bank, GPIO_REG_STAT); in mt7621_gpio_irq_bank_handler()
111 mtk_gpio_w32(bank, GPIO_REG_STAT, pending); in mt7621_gpio_irq_bank_handler()
[all …]
H A Dgpio-tegra.c64 unsigned int bank; member
114 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, in tegra_gpio_compose() argument
117 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); in tegra_gpio_compose()
218 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; in tegra_gpio_set_debounce() local
235 spin_lock_irqsave(&bank->dbc_lock[port], flags); in tegra_gpio_set_debounce()
236 if (bank->dbc_cnt[port] < debounce_ms) { in tegra_gpio_set_debounce()
238 bank->dbc_cnt[port] = debounce_ms; in tegra_gpio_set_debounce()
240 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); in tegra_gpio_set_debounce()
293 struct tegra_gpio_bank *bank; in tegra_gpio_irq_set_type() local
298 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; in tegra_gpio_irq_set_type()
[all …]
/linux/drivers/mtd/nand/raw/
H A Ddenali.h18 #define DEVICE_RESET__BANK(bank) BIT(bank) argument
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) argument
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) argument
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) argument
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) argument
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) argument
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) argument
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) argument
255 #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8) argument
308 int bank; member

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