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Searched refs:anatop_base (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/imx/
H A Dclk-imx8mp.c412 void __iomem *anatop_base, *ccm_base; in imx8mp_clocks_probe() local
416 anatop_base = devm_of_iomap(dev, np, 0, NULL); in imx8mp_clocks_probe()
418 if (WARN_ON(IS_ERR(anatop_base))) in imx8mp_clocks_probe()
419 return PTR_ERR(anatop_base); in imx8mp_clocks_probe()
441 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
442 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
443 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
444 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
445 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
446 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
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H A Dclk-vf610.c56 #define PFD_PLL1_BASE (anatop_base + 0x2b0)
57 #define PFD_PLL2_BASE (anatop_base + 0x100)
58 #define PFD_PLL3_BASE (anatop_base + 0xf0)
59 #define PLL1_CTRL (anatop_base + 0x270)
60 #define PLL2_CTRL (anatop_base + 0x30)
61 #define PLL3_CTRL (anatop_base + 0x10)
62 #define PLL4_CTRL (anatop_base + 0x70)
63 #define PLL5_CTRL (anatop_base + 0xe0)
64 #define PLL6_CTRL (anatop_base + 0xa0)
65 #define PLL7_CTRL (anatop_base + 0x20)
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H A Dclk-imx93.c278 void __iomem *base, *anatop_base; in imx93_clocks_probe() local
306 anatop_base = devm_of_iomap(dev, np, 0, NULL); in imx93_clocks_probe()
308 if (WARN_ON(IS_ERR(anatop_base))) { in imx93_clocks_probe()
309 ret = PTR_ERR(anatop_base); in imx93_clocks_probe()
314 anatop_base + 0x1000, in imx93_clocks_probe()
316 clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200, in imx93_clocks_probe()
318 clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400, in imx93_clocks_probe()
H A Dclk-imx6sl.c103 static void __iomem *anatop_base; variable
132 if ((readl_relaxed(anatop_base + PLL_ARM) & in imx6sl_get_arm_divider_for_wait()
146 saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
149 writel_relaxed(val, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
150 while (!(readl_relaxed(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) in imx6sl_enable_pll_arm()
153 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
206 anatop_base = base; in imx6sl_clocks_init()
H A Dclk-imx6q.c396 static void disable_anatop_clocks(void __iomem *anatop_base) in disable_anatop_clocks() argument
401 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); in disable_anatop_clocks()
408 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); in disable_anatop_clocks()
411 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); in disable_anatop_clocks()
413 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); in disable_anatop_clocks()
416 reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); in disable_anatop_clocks()
418 writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); in disable_anatop_clocks()
439 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
461 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
644 disable_anatop_clocks(anatop_base); in imx6q_clocks_init()
/linux/arch/arm/mach-imx/
H A Danatop.c97 void __iomem *anatop_base; in imx_init_revision_from_anatop() local
104 anatop_base = of_iomap(np, 0); in imx_init_revision_from_anatop()
105 WARN_ON(!anatop_base); in imx_init_revision_from_anatop()
110 digprog = readl_relaxed(anatop_base + offset); in imx_init_revision_from_anatop()
111 iounmap(anatop_base); in imx_init_revision_from_anatop()