Searched refs:active_planes (Results 1 – 11 of 11) sorted by relevance
15 u8 active_planes[I915_MAX_DBUF_SLICES]; member 71 old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice]) in intel_dbuf_bw_changed() 113 dbuf_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw() 168 num_active_planes += hweight8(dbuf_bw->active_planes[slice]); in intel_dbuf_bw_min_cdclk()
508 crtc_state->active_planes &= ~BIT(plane->id); in intel_plane_set_invisible() 521 crtc_state->active_planes &= ~BIT(plane->id);779 new_crtc_state->active_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state() 1684 crtc_state->active_planes |= BIT(y_plane->id); in intel_joiner_add_affected_planes() 1733 if (crtc_state->active_planes & BIT(y_plane->id))1911 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);1912 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
143 return (crtc_state->active_planes & in is_hdr_mode() 603 * unique ids, hence we can use that to reconstruct active_planes. in intel_plane_fixup_bitmasks() 606 crtc_state->active_planes = 0; in intel_plane_fixup_bitmasks() 611 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); in intel_plane_fixup_bitmasks() 635 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && in intel_plane_disable_noatomic() 658 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic() 835 crtc_state->active_planes & BIT(PLANE_CURSOR) && in intel_async_flip_vtd_wa() 925 return is_enabling(active_planes, old_crtc_state, new_crtc_state); in vrr_params_changed() 934 return is_disabling(active_planes, old_crtc_state, new_crtc_state);5653 crtc_state->update_planes |= crtc_state->active_planes; in intel_modeset_all_pipes_late() [all...]
3207 !new_crtc_state->active_planes || in intel_psr_post_plane_update() 3258 psr->enabled && !crtc_state->active_planes);3263 if (!crtc_state->active_planes) {
1278 u8 active_planes;1277 u8 active_planes; global() member
2174 return crtc_state->active_planes & BIT(plane->id) || in intel_color_add_affected_planes()
36 int active_planes; member
408 state->active_planes = cur->active_planes; in amdgpu_dm_crtc_destroy_state() 589 dm_new_crtc_state->active_planes = 0; in amdgpu_dm_crtc_count_crtc_active_planes() 594 dm_new_crtc_state->active_planes = in amdgpu_dm_crtc_count_crtc_active_planes()
1011 int active_planes;993 int active_planes; global() member
699 vrr_active, acrtc->dm_irq_params.active_planes); in dm_crtc_high_irq() 740 * If there aren't any active_planes then DCH HUBP may be clock-gated. in dm_crtc_high_irq() 751 acrtc->dm_irq_params.active_planes == 0) { in dm_crtc_high_irq() 10070 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; in amdgpu_dm_commit_planes() 10315 if (acrtc_state->active_planes == 0 && in amdgpu_dm_commit_planes() 10519 acrtc_state->active_planes > 0) { in amdgpu_dm_commit_streams() 10535 } else if (cursor_update && acrtc_state->active_planes > 0) { in amdgpu_dm_commit_streams() 10546 if ((planes_count || acrtc_state->active_planes == 0) && in amdgpu_dm_commit_streams() 10616 if (dm_old_crtc_state->active_planes ! in amdgpu_dm_commit_streams() [all...]
191 struct vkms_plane_state **active_planes; member