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Searched refs:_gate (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/clk/sunxi-ng/
H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
21 .enable = _gate, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
33 .enable = _gate, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
45 .enable = _gate, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
61 .enable = _gate, \
72 _gate, _prediv, _flags) \ argument
74 .enable = _gate, \
[all …]
H A Dccu_div.h89 _table, _gate, _flags) \ argument
93 .enable = _gate, \
132 _gate, _flags) \ argument
134 .enable = _gate, \
151 _gate, _flags) \ argument
153 .enable = _gate, \
168 _gate, _flags) \ argument
173 _gate, _flags)
178 _gate, _flags) \ argument
183 _gate, _flags)
[all …]
H A Dccu_nm.h43 _gate, _lock, _flags) \ argument
45 .enable = _gate, \
66 _gate, _lock, _flags) \ argument
68 .enable = _gate, \
91 _gate, _lock, _flags) \ argument
93 .enable = _gate, \
119 _gate, _lock, _flags, \ argument
122 .enable = _gate, \
149 _gate, _lock, _flags) \ argument
158 _gate, _lock, _flags, \
[all …]
H A Dccu_mux.h50 _reg, _shift, _width, _gate, \ argument
53 .enable = _gate, \
67 _width, _gate, _flags) \ argument
70 _width, _gate, _flags, \
74 _reg, _shift, _width, _gate, \ argument
78 _width, _gate, _flags, 0)
81 _shift, _width, _gate, _flags) \ argument
83 _reg, _shift, _width, _gate, \
92 _shift, _width, _gate, _flags) \ argument
94 .enable = _gate, \
[all …]
H A Dccu_mp.h38 _gate, _postdiv, _flags) \ argument
40 .enable = _gate, \
59 _gate, _flags) \ argument
61 .enable = _gate, \
89 _gate, _flags) \ argument
91 .enable = _gate, \
119 _gate, _flags) \ argument
121 .enable = _gate, \
H A Dccu_nkm.h41 _gate, _lock, _flags) \ argument
43 .enable = _gate, \
62 _gate, _lock, _flags) \ argument
64 .enable = _gate, \
H A Dccu_nk.h36 _gate, _lock, _postdiv, \ argument
39 .enable = _gate, \
H A Dccu_nkmp.h40 _gate, _lock, _flags) \ argument
42 .enable = _gate, \
H A Dccu_mult.h46 _mshift, _mwidth, _gate, _lock, \ argument
49 .enable = _gate, \
/linux/drivers/clk/mediatek/
H A Dclk-mux.h43 _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ argument
53 .gate_shift = _gate, \
64 _gate, _upd_ofs, _upd, _flags, _ops) \ argument
68 _gate, _upd_ofs, _upd, _flags, _ops) \
72 _width, _gate, _upd_ofs, _upd, _flags, _ops) \ argument
76 _gate, _upd_ofs, _upd, _flags, _ops) \
83 _gate, _upd_ofs, _upd, _flags) \ argument
86 _gate, _upd_ofs, _upd, _flags, \
91 _shift, _width, _gate, _upd_ofs, _upd, _flags) \ argument
94 _shift, _width, _gate, _upd_ofs, _upd, _flags, \
[all …]
H A Dclk-mtk.h113 _width, _gate, _flags, _muxflags) { \ argument
120 .gate_shift = _gate, \
133 _gate, _flags) \ argument
135 _shift, _width, _gate, _flags, 0)
141 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
143 _gate, CLK_SET_RATE_PARENT)
H A Dclk-mt6795-topckgen.c21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
24 _gate, 0, -1, _flags)
26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
28 _gate, CLK_SET_RATE_PARENT | _flags)
H A Dclk-mt8173-topckgen.c22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
25 _gate, 0, -1, _flags)
27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
29 _gate, CLK_SET_RATE_PARENT | _flags)
/linux/drivers/clk/actions/
H A Dowl-composite.h38 _mux, _gate, _div, _flags) \ argument
41 .gate_hw = _gate, \
53 _gate, _div, _flags) \ argument
55 .gate_hw = _gate, \
67 _mux, _gate, _factor, _flags) \ argument
70 .gate_hw = _gate, \
82 _gate, _mul, _div, _flags) \ argument
84 .gate_hw = _gate, \
98 _mux, _gate, _flags) \ argument
101 .gate_hw = _gate, \
/linux/scripts/gcc-plugins/
H A Dgcc-generate-rtl-pass.h42 #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate)
H A Dgcc-generate-simple_ipa-pass.h42 #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate)
H A Dgcc-generate-gimple-pass.h42 #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate)
H A Dgcc-generate-ipa-pass.h106 #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate)
/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c680 #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate) argument
1266 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\ argument
1272 .cfg = (struct stm32_gate_cfg *) {_gate},\
1276 #define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\ argument
1282 .cfg = (struct stm32_gate_cfg *) {_gate},\
1368 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ argument
1376 _gate,\
/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c1206 #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \ argument
1215 .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
1216 &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \
/linux/drivers/clk/thead/
H A Dclk-th1520-ap.c78 #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ argument
80 .enable = _gate, \
/linux/drivers/clk/
H A Dclk-stm32f4.c521 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) argument